ja2bo2t
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We are working in a 0.35um TSMC technology and I have been using the Tanner Hi-ESD Pad library as a guide for designing our pads (digital I and O, analog references, analog out, and power). In this library, and the others that I can find online, the pad is normally only connected to using M1, and it is normally only about a ~20um trace opening to ~40um through 45 degree angles at the pad. On chip we are using a 80um width power bus on M2 and M3; is there any reason why the pad cannot be connected to on M2 and M3? Is it for the ESD protection circuitry?