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##### Junior Member level 2

Here it is my component:

Code:

```
entity barrel_shifter is
Generic ( N : integer := 4);
Port ( data_in : in STD_LOGIC_VECTOR (N-1 downto 0);
shift : in STD_LOGIC_VECTOR (integer(ceil(log2(real(N))))-1 downto 0); -- log2 of N => number of inputs for the shift
data_out : out STD_LOGIC_VECTOR (N-1 downto 0));
end barrel_shifter;
```

Code:

```
entity mux is
Generic ( N : integer := 4);
Port ( data_in : in STD_LOGIC_VECTOR (N-1 downto 0);
sel : in STD_LOGIC_VECTOR (integer(ceil(log2(real(N))))-1 downto 0); -- log2 of N => number of inputs for the shift
data_out : out STD_LOGIC);
end mux;
architecture Behavioral of mux is
begin
data_out <= data_in(to_integer(unsigned(sel)));
end Behavioral;
```

But how can I realize in VHDL something like that? If I hadn't STD_LOGIC_VECTOR as input it would be easy, but I need to make a generic Barrel Shifter (with generic map construct), so I can't manually connect each wire because I don't know the value of the generic N.

In my barrel_shifter entity I tried this:

Code:

```
architecture Structural of barrel_shifter is
signal q : STD_LOGIC_VECTOR (N-1 downto 0);
begin
connections: for i in 0 to N-1 generate
mux: entity work.mux(Behavioral) generic map(N) port map(std_logic_vector(unsigned(data_in) srl 1), shift, q(i));
end generate connections;
data_out <= q;
end Structural;
```

Code:

`data_tmp := data_in(i downto 0) & data_in(N-i downto 1);`