tanish
Junior Member level 2
Hello,
I'm trying to send and receive data to/from fpga using ft232rl module(rs232). I'm using mojo v3(spartan 6 lx9). however I have tried to produce baud rate and receiver module, I'm not able to receive data from ft232rl.
my baud generator is like this:
as the clock frequency is 50 Mhz I tried to produce one tick in every 28 clocks. (50000000/(16 * 115200)) = 27.126
then I wrote the reading module as follow:
and then:
and I'm using pyserial library to transmit data. I can see the green LED of ft232 module when I send a data like 0x35 but there is any change in FPGA board.
could anyone help me? I really need this.
I'm trying to send and receive data to/from fpga using ft232rl module(rs232). I'm using mojo v3(spartan 6 lx9). however I have tried to produce baud rate and receiver module, I'm not able to receive data from ft232rl.
my baud generator is like this:
PHP:
module baud( clk, rxclk_en );
input clk;
output rxclk_en;
reg [12:0] rx_acc = 13'h0000;
reg tmp = 1'b0;
always @(posedge clk)
begin
if (rx_acc == 13'h1ff5) begin
rx_acc <= 13'b0000000000000;
tmp <= 1'b1; end
else begin
rx_acc <= rx_acc + 9'h12f;
tmp <= 1'b0; end
end
assign rxclk_en = tmp;
endmoduleas the clock frequency is 50 Mhz I tried to produce one tick in every 28 clocks. (50000000/(16 * 115200)) = 27.126
then I wrote the reading module as follow:
PHP:
module rx ( clk, din, ready, D_out );
input clk, din;
output [7:0] D_out;
output ready;
reg rdy;
reg [7:0] dout = 8'b11111111;
wire clk_en;
baud a0 ( clk, clk_en );
reg [4:0] cnt = 5'b00000;
reg [3:0] state = 4'b0000;
always @ (posedge clk)
if (clk_en)
begin
case(state)
4'b0000: begin
rdy = 1'b0;
if ( din == 1'b0 && cnt == 4'b0110 ) begin
state <= 4'b0001;
cnt <= 4'b0001; end
else
state <= 4'b0000;
if (din == 1'b0)
cnt <= cnt + 1'b1;
else
cnt <= cnt + 1'b0; end
4'b0001: begin
if (cnt == 4'b1111) begin
state <= 4'b0010;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b0010: begin
if (cnt == 4'b1111) begin
state <= 4'b0011;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b0011: begin
if (cnt == 4'b1111) begin
state <= 4'b0100;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b0100: begin
if (cnt == 4'b1111) begin
state <= 4'b0101;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b0101: begin
if (cnt == 4'b1111) begin
state <= 4'b0110;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b0110: begin
if (cnt == 4'b1111) begin
state <= 4'b0111;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b0111: begin
if (cnt == 4'b1111) begin
state <= 4'b1000;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b1000: begin
if (cnt == 4'b1111) begin
state <= 4'b1001;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b1001: begin
if (cnt == 4'b1111) begin
state <= 4'b1010;
cnt <= 4'b0000;
dout <= {din,dout[7:1]}; end
else
cnt <= cnt + 1'b1; end
4'b1010: begin
rdy = 1'b1;
if (cnt == 4'b1111) begin
state <= 4'b0000;
cnt <= 4'b0000; end
else
cnt <= cnt + 1'b1; end
endcase
end
assign D_out = dout;
assign ready = rdy;
endmoduleand then:
PHP:
module LED( clk, rx, LED);
input clk, rx;
output reg [7:0] LED;
wire rdy;
wire [7:0] D_out;
test b0 ( clk, rx, rdy, D_out );
always @ (posedge clk)
begin
if (rdy)
LED = D_out;
endand I'm using pyserial library to transmit data. I can see the green LED of ft232 module when I send a data like 0x35 but there is any change in FPGA board.
could anyone help me? I really need this.