hyleeinhit
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Hi, folks,
I want to know the effect of connecting an OTA directly to PAD without buffer. The OTA is folded cascoded structure as shown in attachment. Transistors N2 and N3 provide 500nA bias current, respectively. This OTA output is also connecting to a transistor gate in the following stage.
I need to connect this OTA directly to PAD, but I am worried about the effect from the pad leakage current, pad parasitic capacitance and bonding parasitic capacitance and inductance.
Two options of PADs:
1. PAD with ESD protection. Leakage current exists with such a PAD. I have a PAD protected by a 333um2 area diode. How much is the leakage current of PAD. Can my OTA drive it?
2. PAD without ESD protection. No leakage current exists but having risk of breakdown. Anyone recommend such a PAD? FYI, I am a student and not developing a product.
Effect from pad parasitic capacitance and bonding parasitic capacitance and inductance:
How much is the typical value of these capacitance?
I want to know the effect of connecting an OTA directly to PAD without buffer. The OTA is folded cascoded structure as shown in attachment. Transistors N2 and N3 provide 500nA bias current, respectively. This OTA output is also connecting to a transistor gate in the following stage.
I need to connect this OTA directly to PAD, but I am worried about the effect from the pad leakage current, pad parasitic capacitance and bonding parasitic capacitance and inductance.
Two options of PADs:
1. PAD with ESD protection. Leakage current exists with such a PAD. I have a PAD protected by a 333um2 area diode. How much is the leakage current of PAD. Can my OTA drive it?
2. PAD without ESD protection. No leakage current exists but having risk of breakdown. Anyone recommend such a PAD? FYI, I am a student and not developing a product.
Effect from pad parasitic capacitance and bonding parasitic capacitance and inductance:
How much is the typical value of these capacitance?
Attachments
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