High rate ADCs designed to connect to an FPGA will typically send data with multiple samples per cycle.
For example, 3.6Gsps @ 8b is a little less than 32Gbps. This could be done using 4 10Gbps lanes, or 32 1Gbps lanes. In the FPGA fabric, this might be 9 8b samples per 500MHz cycle, or 18 8b samples per 250MHz cycle.
As a result, FIR filters, mixers, decimators, and slow-control loops make sense at these high rates. Things like IIR filters are much more difficult.