sai_shashi
Junior Member level 3
HI there,
I am preparing for VLSI interviews. When i was studying on skewed gates i got this doubt that how downsizing the nMOS will favor the rising o/p transition and downsizing pMOS will favour falling o/p transition? I am really confused. Can someone please give me an intuitive understanding on this?
Thanks
I am preparing for VLSI interviews. When i was studying on skewed gates i got this doubt that how downsizing the nMOS will favor the rising o/p transition and downsizing pMOS will favour falling o/p transition? I am really confused. Can someone please give me an intuitive understanding on this?
Thanks