Confusion regarding HI skew and LO skew gates.

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sai_shashi

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HI there,
I am preparing for VLSI interviews. When i was studying on skewed gates i got this doubt that how downsizing the nMOS will favor the rising o/p transition and downsizing pMOS will favour falling o/p transition? I am really confused. Can someone please give me an intuitive understanding on this?

Thanks
 

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