matrixofdynamism
Advanced Member level 2
I have a recursive equation where the next output is a function of the current output and a constant set before start of the iteration. I am trying to implement this in hardware using VHDL. The aim is to see how many iterations are required to reach a specific value. At start I take a value 0, square it using multiplier and then add it to a constant. This result becomes new input for the squarer. This squaring and adding squared result to constant which becomes new input for the squarer will happen until either the result reaches a threshold or 256 iterations are complete.
I know that the multiplier blocks in Altera Quartus have option for adding pipeline latency. This shall let me run the design at a higher clock frequency as far as I am aware.
There is a problem, since the output is actually fed back, if I use pipelining, I will not get an increased throughput. Lets say I have N stages in pipeline. At start I have to wait N cycles to get first output, that feeds back in and I get next output N cycles later and so on. It is not possible to get a new result every clock cycle. Is there a workaround for this when using recursion or feedback like this?
I know that the multiplier blocks in Altera Quartus have option for adding pipeline latency. This shall let me run the design at a higher clock frequency as far as I am aware.
There is a problem, since the output is actually fed back, if I use pipelining, I will not get an increased throughput. Lets say I have N stages in pipeline. At start I have to wait N cycles to get first output, that feeds back in and I get next output N cycles later and so on. It is not possible to get a new result every clock cycle. Is there a workaround for this when using recursion or feedback like this?
