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Confusion about blocking and nonblocking assignment?

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jason7361

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Hi! I have confusion about blocking and nonblocking assignment in the Verilog,
can anyone answer the following question for me?

A = 1;
B = 0;
C <= A;
B = C;
#5 D = B;
#5 D = C;
A <= D;

I am not sure the code above is valid, but if it is valid, what's the value of A,B,C,D at different time?

Thank you.
 

FvM

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The code is not valid, because you can't mix both assignment types for the same signal.

I noticed, that the link for the popular cummings paper on non-blocking assignments has expired. Here's a copy:
 
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