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Confused on the PMOS biasing.......

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Anachip

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Hi Guys,

Currently im designing an opamp for my design familiriaty. If you noticed from my schematic there are 2 PMOS biasing. For bias1, i believe what i have done is correct that is I biasing them according to W/L ratio. But as for bias2, i believe that biasing shouldn't be like that as the VGS is not same at the two points. Actually i need a biasing bias1=1.1V and bias2=1.0V. So, i meeting some problem here on designing the current mirror biasing for the 2 pmos. Please guide me how do I overcome the issue.

Thanks,
Anachip
 

lavitaebelle

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your scheme of biasing is not right in the first place.
You are biasing your load transistors by means of both bias voltages and also through tail current source. You must do one of the two. if you are biasing these transistors using some bias voltage then you must not connect them in a diode fashion and vice versa.

Assuming they are voltage biased, there are lots of methods of biasing them. You can refer to any analog circuit design book (like Johns and Martin, Razavi) for biasing schemes. The simplest bias is to use two stacked diode connected pmos transistors identical to the load pmos transistors, driven by a current source.

This is not the greatest method as it limits the swing on your circuit. You can look up for wide swing current mirrors.
 

montage2000

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tuing the w/l to guarentee all work in saturation region
 

vonleo

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why to bias the mirror if a current source is used?
 

cicer

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lavitaebelle' is right. the pmos is as load.
your words"VGS is not same at the two points" is error.
 

plasma2000

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VDS=1.1-1.0 = 0.1 Volt, too small?
 

ccw27

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You shouldnt need any bias. Its self-bias.
 

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