The latter is correct, simply for physical/electrical reason: N+NW GR is to be connected to the most positive potential (VDD), so attracts and absorbs electrons because of their negative charge (and rejects holes because of their positive charge).... someone else also told me that N+NW GR absorb electron and P+ GR absorbs hole.
The latter is correct, simply for physical/electrical reason: N+NW GR is to be connected to the most positive potential (VDD), so attracts and absorbs electrons because of their negative charge (and rejects holes because of their positive charge).
P+ GR is to be connected to the most negative potential (VSS or GND), hence attracts and absorbs holes (and rejects electrons).
But this is essentially done to prevent the latchup problem right? I mean there will be a low resistance path from power supply VDD to GND. To eliminate this short circuit we use these n+ and p+ guard rings.
Isnt it?
The latter is correct, simply for physical/electrical reason: N+NW GR is to be connected to the most positive potential (VDD), so attracts and absorbs electrons because of their negative charge (and rejects holes because of their positive charge).
P+ GR is to be connected to the most negative potential (VSS or GND), hence attracts and absorbs holes (and rejects electrons).
Yes, you're right. I just wanted to explain the physical reason.
Another intention/application for using guard rings is screening of/against capacitive or inductive coupling of spikes/noise (via substrate or from adjacent high energy switching stages), or screening of low-noise input stages.
Between N+NW and PSUB, there is a reverse-biased diode, how does this structure absorb noise electron? And the same question is true for P+ and PSUB.
Erikl, how does this double GR screen of the cap/ind induced coupling noise? Is it the same with that in latch up?
Please tell me if I'm right:
(1) P+ on substrate connected to GND and N+ on NW connected to VDD act as hole and electron absorber;
(2) Electrons are drifted to (absorbed by) VDD through diode between N+NW and substrate;
(3) Holes are drifted to (absorbed by) GND through diode between P+ and substrate;
(4) P+ on sub and N+ on NW also work as screening: block inside/outside electrical noise source penetration.
Besides, I have further questions about this topic.
1) Is there any sequence for double GRs? ie. external ring for N+NW and internal ring for P+, or vice versus. If yes, which one is correct or better?
Yes.2) Is such sequence the same for the aggressor block and viticm block?
3) Can we use N+ on sub connected to VDD and P+ on NW connected to GND as GR as dick_freebird said above
(3) There is no diode between P+ and substrate!
(3) Holes (within the space charge region of the diode) are drifted to (absorbed by) GND through diode between N+NW and substrate;
In the former case I'd use N+ on NW on sub conn. to VDD to achieve a wider space charge region
I think there is weak diode between P+ and psub because compared to P+, doping density of psub is much lower than P+ (or psub is seen as a week N compared to P+). is it Right?
Holes you mentioned here (inside space charge region of the diode) is not the noisy holes caused by switching of adjacent circuit, isn't it? And what I mean is since noisy electron are absorbed by VDD through diode, then the noisy holes will be absorbed by GND through the above weak diode. (sounds not very persuasive. Hope you understand what I'm explaining)
N+ on NW on sub? or just N+ on sub? any difference between them? I seldom see the latter as GR during my past jobs.
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?