Confused about the Role of N+ and P+ Guard Ring

[waosai]

Hi everyone, I have a question concerning the role of the guard ring.
Someone told me that N+NW GR blocks electron and P+ GR absorbs electron. But someone else also told me that N+NW GR absorb electron and P+ GR absorbs hole.
I'm so confused about the role of this two GR. Can anyone tell me how this two GR's work (absorb/block electron/hole?)
Thanks a lot !

 

[Prashanth.vinnakota]

Guard rings are essentially used to prevent LatchUp problem in VLSI.

Refer to Latchup prevention techniques. You can get the explanation.

All the best.

 

[erikl]

... someone else also told me that N+NW GR absorb electron and P+ GR absorbs hole.

The latter is correct, simply for physical/electrical reason: N+NW GR is to be connected to the most positive potential (VDD), so attracts and absorbs electrons because of their negative charge (and rejects holes because of their positive charge).

P+ GR is to be connected to the most negative potential (VSS or GND), hence attracts and absorbs holes (and rejects electrons).

 

[Prashanth.vinnakota]

The latter is correct, simply for physical/electrical reason: N+NW GR is to be connected to the most positive potential (VDD), so attracts and absorbs electrons because of their negative charge (and rejects holes because of their positive charge).

P+ GR is to be connected to the most negative potential (VSS or GND), hence attracts and absorbs holes (and rejects electrons).

Hi erikl. Your explanation was correct.

But this is essentially done to prevent the latchup problem right? I mean there will be a low resistance path from power supply VDD to GND. To eliminate this short circuit we use these n+ and p+ guard rings.
Isnt it?

 

[erikl]

But this is essentially done to prevent the latchup problem right? I mean there will be a low resistance path from power supply VDD to GND. To eliminate this short circuit we use these n+ and p+ guard rings.
Isnt it?

Yes, you're right. I just wanted to explain the physical reason.

Another intention/application for using guard rings is screening of/against capacitive or inductive coupling of spikes/noise (via substrate or from adjacent high energy switching stages), or screening of low-noise input stages.

 

[dick_freebird]

The guardring can serve in multiple ways.

A P+ ring in psub is simply a superior ohmic connection,
ties the region together and to some current-return
point. It also creates a highly doped region which will
not invert even if the substrate does, eliminating
surface conduction (field NMOS being susceptible to
mobile ion and radiation induced leakage).

A reverse biased N+ ring in psub forms a depletion
region which will sweep out any carrier that diffuses
into it. This is why you'll often see nested guardrings
of alternating type in ESD structures - you want to
pull back out any carriers injected by pin overvoltage
so that they can't wander into the less-well-protected
core circuitry (often entirely lacking, or sparsely
"tapped" with same-species plugs).

The contrary cases hold true for the N- well and so
on.

 

[arun2011]

A P+ ring in psub is simply a superior ohmic connection,
ties the region together and to some current-return
point. It also creates a highly doped region which will
not invert even if the substrate does, eliminating
surface conduction (field NMOS being susceptible to
mobile ion and radiation induced leakage).

You mean a P+GR won't collect holes ?? please explain??

A reverse biased N+ ring in psub forms a depletion
region which will sweep out any carrier that diffuses
into it. This is why you'll often see nested guardrings
of alternating type in ESD structures - you want to
pull back out any carriers injected by pin overvoltage
so that they can't wander into the less-well-protected
core circuitry (often entirely lacking, or sparsely
"tapped" with same-species plugs).


If we are using a double GR, is it mandatory to keep the N+GR outside?? Please explain in detail.

 

[waosai]

The latter is correct, simply for physical/electrical reason: N+NW GR is to be connected to the most positive potential (VDD), so attracts and absorbs electrons because of their negative charge (and rejects holes because of their positive charge).

P+ GR is to be connected to the most negative potential (VSS or GND), hence attracts and absorbs holes (and rejects electrons).

Thanks all for replying my question.

But there is still confuse about the latter one: Between N+NW and PSUB, there is a reverse-biased diode, how does this structure absorb noise electron? And the same question is true for P+ and PSUB.

- - - Updated - - -

Yes, you're right. I just wanted to explain the physical reason.

Another intention/application for using guard rings is screening of/against capacitive or inductive coupling of spikes/noise (via substrate or from adjacent high energy switching stages), or screening of low-noise input stages.

Erikl, how does this double GR screen of the cap/ind induced coupling noise? Is it the same with that in latch up?

 

[erikl]

Between N+NW and PSUB, there is a reverse-biased diode, how does this structure absorb noise electron? And the same question is true for P+ and PSUB.

Between N+NW and PSUB, this reverse-biased diode creates a space charge region, which sweeps straying penetrating electrons to VDD, and holes to GND (by "hopping" the them "missing" electrons to VDD).

Erikl, how does this double GR screen of the cap/ind induced coupling noise? Is it the same with that in latch up?

I didn't speak about double GRs -- this was elsewhere. However, any GR connected to the corresponding power rail serves as a screen: Imagine screening a signal wire by adjacent grounded wires on a PCB or a layout: a similar screening effect can be achieved by appropriately connected GRs -- in this case -- due to the width of the space charge region, the effect even works "deeper", i.e. more 3-dimensional than the much more 2-dimensional effect of metal wires on a plain surface.

So GRs can not only absorb charge carriers -- this is their effect against latch-up, but also "ground" electric fields (intruding from both sides), by this screening influenced and -- by appropriate design -- also induced electrical noise, preventing it to penetrate from external sources, or preventing noise produced inside the GR to escape.

 

[waosai]

Thank you very much, erikl. Here is a brief summary of the above discussed contents. Please tell me if I'm right:

(1) P+ on substrate connected to GND and N+ on NW connected to VDD act as hole and electron absorber;
(2) Electrons are drifted to (absorbed by) VDD through diode between N+NW and substrate;
(3) Holes are drifted to (absorbed by) GND through diode between P+ and substrate;
(4) P+ on sub and N+ on NW also work as screening: block inside/outside electrical noise source penetration.

Besides, I have further questions about this topic.

1) Is there any sequence for double GRs? ie. external ring for N+NW and internal ring for P+, or vice versus. If yes, which one is correct or better?
2) Is such sequence the same for the aggressor block and viticm block?
3) Can we use N+ on sub connected to VDD and P+ on NW connected to GND as GR as dick_freebird said above

Thanks!

 

[erikl]

Please tell me if I'm right:

(1) P+ on substrate connected to GND and N+ on NW connected to VDD act as hole and electron absorber;
(2) Electrons are drifted to (absorbed by) VDD through diode between N+NW and substrate;
(3) Holes are drifted to (absorbed by) GND through diode between P+ and substrate;
(4) P+ on sub and N+ on NW also work as screening: block inside/outside electrical noise source penetration.

(3) There is no diode between P+ and substrate!
(3) Holes (within the space charge region of the diode) are drifted to (absorbed by) GND through diode between N+NW and substrate;

The other items are ok, I think.

Besides, I have further questions about this topic.

1) Is there any sequence for double GRs? ie. external ring for N+NW and internal ring for P+, or vice versus. If yes, which one is correct or better?

The inner GR usually is the tap contact GR, i.e. P+ on substrate conn. to GND, resp. N+ on NW conn. to VDD .

An optional second outer GR would then be N+ on NW conn. to VDD around the inner P+ on substrate GR conn. to GND,
resp. a P+ GR on substrate conn. to GND around the NW region with its inner N+ on NW GR conn. to VDD
or a P+ GR on NW conn. to GND around the inner N+ on NW GR conn. to VDD .

2) Is such sequence the same for the aggressor block and viticm block?

Yes.

3) Can we use N+ on sub connected to VDD and P+ on NW connected to GND as GR as dick_freebird said above

Yes. In the former case I'd use N+ on NW on sub conn. to VDD to achieve a wider space charge region.

 

[waosai]

(3) There is no diode between P+ and substrate!

I think there is weak diode between P+ and psub because compared to P+, doping density of psub is much lower than P+ (or psub is seen as
a week N compared to P+). is it Right?

(3) Holes (within the space charge region of the diode) are drifted to (absorbed by) GND through diode between N+NW and substrate;

Holes you mentioned here (inside space charge region of the diode) is not the noisy holes caused by switching of adjacent circuit, isn't it? And what I mean is since
noisy electron are absorbed by VDD through diode, then the noisy holes will be absorbed by GND through the above weak diode. (sounds not very persuasive. Hope you
understand what I'm explaining)

In the former case I'd use N+ on NW on sub conn. to VDD to achieve a wider space charge region

N+ on NW on sub? or just N+ on sub? any difference between them? I seldom see the latter as GR during my past jobs.

 

[erikl]

I think there is weak diode between P+ and psub because compared to P+, doping density of psub is much lower than P+ (or psub is seen as a week N compared to P+). is it Right?

No, you can't designate psub as a weak N: a p-doping stays a p-doping; there's only a small shift between the 2 energy band levels -- you can't call this a diode -- not even a weak one.

Holes you mentioned here (inside space charge region of the diode) is not the noisy holes caused by switching of adjacent circuit, isn't it? And what I mean is since noisy electron are absorbed by VDD through diode, then the noisy holes will be absorbed by GND through the above weak diode. (sounds not very persuasive. Hope you understand what I'm explaining)

You should differentiate between intruding charge carriers (electrons & holes) and impinging electric or magnetic fields.

I wouldn't designate the former ones (electrons & holes) as "noisy" -- even if one could consider their contribution by movement in an electric field as noise -- they are straying (i.e. randomly present) charge carriers injected by any (nearby) forward diode and diffusing or drifting into another electric field. These should drift and be absorbed by the bulk tap GRs in order not to contribute to possible latch-up. The electric field of a reverse diode is needed to trap them.

Intruding electric (by influence, ie. capacitive coupling) or magnetic (by induction, i.e. inductive coupling) fields may contribute real noise by their influence or induction effect. That's why they should be screened, i.e grounded by a low-ohmic GR, be it p+ on sub or n+ on nwell: here, no reverse diode field is needed, just the low-ohmic connection to (virtual) GND.

N+ on NW on sub? or just N+ on sub? any difference between them? I seldom see the latter as GR during my past jobs.

I told you above: with N+ on NW on sub -- due to lower NW doping -- you create a somewhat wider space charge region with the chance to catch more straying charge carriers. Its disadvantage is, however, that it needs more real estate (area).

 

[waosai]

Thank you for your patient explanation these days, erikl. I thought I have understand the usage of GR which is such a common isolation technique in IC design.
But it's far from what I understand. Thank you again!