COnformal Ultra LVR (final SPICE netlist)

[nohj_yar]

Hi all!

Im new on using the cadence tool COnformal Ultra LVR. It says that "Conformal LVR enables formal verification of the final SPICE netlist against the golden RTL or final gate-level netlist to ensure that the design taped out is functionally equivalent with golden RTL and the final gate-level netlist."

My question is that what is the structure of the final SPICE netlist stated above? What is the difference between full chip netlist of an FPGA? Difference between full chip netlist of ASIC?

Thanks..

 

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My question is that what is the structure of the final SPICE netlist stated above?

I wouldn't know, I haven't worked on ASICs for 10 years. Seems all the tools are different now.

What is the difference between full chip netlist of an FPGA? Difference between full chip netlist of ASIC?

An FPGA netlist isn't a SPICE netlist, Xilinx/Altera/etc already designed the chip at the gate level. The contents of a Xilinx netlist are LUTs, FF, PLL, MMCM, DSP blocks, block memory, I/O, etc. macros either in EDIF, Verilog, or VHDL. There are no ASIC like gates or transistors as the primitives in an FPGA design are much more granular.