Conformal lec-abort points,blackbox mismatch,cutpoint

[sabucheeru27@gmail.com]

HAI ALL,

Can anyone help me please........
I have started my career just 4 months back,I'm doing the functionality check(rtl vs netlist) for the first time and using CONFORMAL LEC tool.
I have used hierarchial comparison and have 3 doubts at present

1.After comparison I got some abort points.And when I went into its schematic,both the rtl and netlist have dffs with their clock port driven with NA(instead of 0 or 1).What is this NA and How to resolve Abort points?.

2.The other non equivalency were the CUTS.Will the non equivalent CUTs make any functionality mismatch?Can that be neglected?

3.I have some modules with non equivalent BLACKBOXES[which were not blackboxed by me(not user defined)] How can I resolve this?Will the non equivalent blackboxes cause functionality mismatch?There are no un equivalent PI,PO and DFF,so will the netlist will be functionally equal with RTL?

Please do reply......

 

[dftrtl]

1) Abort Points do come because of large fanin logic cone and if you have not used few RTL rules like using X in RTL.

2) In some cases.

3) You need to figure out first why they have got blackboxed. They are also important.

 

[sabucheeru27@gmail.com]

1) Abort Points do come because of large fanin logic cone and if you have not used few RTL rules like using X in RTL.

2) In some cases.

3) You need to figure out first why they have got blackboxed. They are also important.

1,Can you please tell me how to figure out that why they have blackboxed? Will blackboxed modules cause any functional mismatch??How can I resolve un equivalent blackboxes(that are not user defined,its tool defined)?
2,What are those NA in the schematics(in the case of abort points)??
3,How can I resolve abort points??What will be the main cause of abort points???
Can you be more specific on all these??? Im still uncleared please......

 

[dftrtl]

Do "REPort BLack Box" and see what it returns.
Analyze what you have supllied for those modules I mean .lib or .v file and un synthesizable code

 

[sabucheeru27@gmail.com]

Do "REPort BLack Box" and see what it returns.
Analyze what you have supllied for those modules I mean .lib or .v file and un synthesizable code

Hi
Now I resolved the aborted points issue,it was the multiplier problem..I used (analyze abort -compare) command and resolved it
I have tried- report black box-but the black boxed things are spram16k,dpram and the mismatch is not that.When i went through non equivalent blackbox that non corresponding support the cause of un equivalence is written as unknown.....the thing is the instance has got black boxedand that instance contains the memory library,that was one datamemory..should I use add notranslate modules command and make that user defined black box since that is a memory??Im using .v simulation libraries...
please help me....i have tried a lot to resolve those...

 

[dftrtl]

Please go ahead and add notranslate on memory modules

 

[sabucheeru27@gmail.com]

Please go ahead and add notranslate on memory modules

Sir
The datamemory is instantiated with one spram library memory module..I add notranslate to spram and still I got 1 non equivalent black box after comparison..Still that datamemory is the blackbox and 1 input pin of it shows mismatch.Can you please be more specific?Since Im a fresher I face some problem to debugg this

 

[amitk3553]

HAI ALL,

Can anyone help me please........
I have started my career just 4 months back,I'm doing the functionality check(rtl vs netlist) for the first time and using CONFORMAL LEC tool.
I have used hierarchial comparison and have 3 doubts at present

1.After comparison I got some abort points.And when I went into its schematic,both the rtl and netlist have dffs with their clock port driven with NA(instead of 0 or 1).What is this NA and How to resolve Abort points?.

2.The other non equivalency were the CUTS.Will the non equivalent CUTs make any functionality mismatch?Can that be neglected?

3.I have some modules with non equivalent BLACKBOXES[which were not blackboxed by me(not user defined)] How can I resolve this?Will the non equivalent blackboxes cause functionality mismatch?There are no un equivalent PI,PO and DFF,so will the netlist will be functionally equal with RTL?

Please do reply......

Yup BB is a serious problem.Need to remove them.
Blackbox are produced in following cases:
1)Either you had not provided any basic gate ,common file or you have provided extra file in lec scripts but not included in synthesis (src_design.lst FILE)
2)Either there is problem in your functionality.You just check parametres and null slices in your design.If you find and remove those null slices by changing parametres.Then your blackboxes will automatically removed

After removing BB ,other problems will automatically be removed

 

[sabucheeru27@gmail.com]

Yup BB is a serious problem.Need to remove them.
Blackbox are produced in following cases:
1)Either you had not provided any basic gate ,common file or you have provided extra file in lec scripts but not included in synthesis (src_design.lst FILE)
2)Either there is problem in your functionality.You just check parametres and null slices in your design.If you find and remove those null slices by changing parametres.Then your blackboxes will automatically removed

After removing BB ,other problems will automatically be removed

Sir,

Actually the thing is,I have 1 instantiation named IDataMemory in which spram16k_16.v memory library is instantiated.Since spram is a memory library the tool blackboxed it.
And the un equivalent bb is the IDataMemory.I couldnt find what exactly is causing the mismatch.Can u please be more specific.Please help me in resolving this..

 

[amitk3553]

Sir,

Actually the thing is,I have 1 instantiation named IDataMemory in which spram16k_16.v memory library is instantiated.Since spram is a memory library the tool blackboxed it.
And the un equivalent bb is the IDataMemory.I couldnt find what exactly is causing the mismatch.Can u please be more specific.Please help me in resolving this..

Friend Either problem is with your instantiation or with memory.Tool is not able to get the internal details of memory.Thats why BB is there.So you have to check it and see the errors regarding BB.There will be cause or error shown in tool window regarding BB.Check that.

 

[sabucheeru27@gmail.com]

Friend Either problem is with your instantiation or with memory.Tool is not able to get the internal details of memory.Thats why BB is there.So you have to check it and see the errors regarding BB.There will be cause or error shown in tool window regarding BB.Check that.

Ya I understand,but the thing is the same spram16k_16 instantiated as idatamemory of anaother dsp has no issue...the connection and instantiation are the same for both....