It's generated after you build (synthesize, place & route) your design using Quartus, Xilinx ISE, or whatever tool you use. For Altera FPGAs, the file will have a .sof extension... I forget what the extension is for Xilinx.
In a lot of situations, the programming is done via JTAG. You'll need a Byteblaster or other cable to connect from your PC's USB port to the JTAG port on the board.
For Xilinx configuration file for FPGA created with *.bin extension,
for Altera with *.sof or *.ptf extension and
for Actel with *.pdb or *.stp extension.