conditional operator and if statement execution are equal in verilog ?

[kommu4946]

Hi all, conditional operator and if statement are equal for the fallowing piece of code..

wire enable1 = (expression1 ==1 && expression2 ==1)?1:0;

always @ (posedge clock) begin
   if (enable1)begin
    statement1;
    statement2;
  end
end

always @ (posedge clock) begin
   if ( (expression1 ==1 && expression2 ==1))begin
    statement1;
    statement2;
  end
end

Are they equal in functionality...? simulations working same..but they are not giving same results on FPGA board? what might be the reason...?

 

[ads-ee]

They should be identical and should result in identical circuits.

Take a look at the pre-synthesis schematic and the post synthesis schematics for both styles of coding it.

The only other thing that may be causing some difference could be something do with the definition of expression1/2 whereby the two options evaluate differently (though I can't see anyway that could happen).

- - - Updated - - -

I think you should show us the real code that is having a problem rather than the pseudo code. It could be something else that is the problem.

 

[sharath666]

Can you check the synthesis report of the failing case and compare it with the corresponding report of the pass case? I am guessing something is optimized away...