moonshine8995
Newbie level 6
Concatination problem in port map in vhdl
i want to port map
out is 32 bit std_logic_vector and mid is 16 bit std_logic_vector.
how should i do this?
i change it to this
but i see this error
thanks.
i want to port map
Code:
out_x=> mid
how should i do this?
i change it to this
Code:
out => (x"0000" &mid)
Code:
Formal "out_x" of mode OUT cannot be associated with an expression.