concatenate problem in vhdl code

[nursafirah]

hye...
i have 1 problem. i don't know what the problem in this conca code.. when i compile,its no error. but when i start to analysis and elaborate, it come out warning. (Warning (10036): Verilog HDL or VHDL warning at compression.vhd(39): object "conca" assigned a value but never read)

below is my code. can anyone please help me..

-- Name: NoC’s Power Optimisation through Packet Compression Technique
-- This code was written by Nursafirah Binti Abdul Razak.  
-- Mei. 12th, 2014 
-- Purpose : compress the bit 
-- After reset signal, it will compress the bit output
--input = 001000110 11110000 11011010 00000001 11111010 01101100 00000001 00001000 (64 bit)
--LUT = 00100110 = 00, 11111010 = 01, 01101100 = 10, 00000001 = 11
--output last = 00 11110000 11011010 11 01 10 11 00001000 (33 bit) 


library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all; 

entity compression is

port (	clk			: in std_logic;
	bitout1, bitout4  : buffer std_logic_vector(1 downto 0);
	bitout2, bitout3	: buffer std_logic_vector(7 downto 0); 
	bitin													  : in std_logic_vector (31 downto 0);
--	a,b,c,d,e,f,g,h									  : in std_logic_vector (7 downto 0);
   busy				   								  : in std_logic;                        --for clock is '1'
   not_ready_a 										  : out std_logic;                      --for clock is '0'
   not_ready_b 										  : out std_logic;  
   not_ready_c 										  : out std_logic;  
   not_ready_d 										  : out std_logic);  
 --  not_ready_e 											  : out std_logic;  
--   not_ready_f 											  : out std_logic;  
--   not_ready_g 											  : out std_logic;
 --  not_ready_h 											  : out std_logic);  	
	
end entity;

-----------------------architecture begin-----------------------------------------

architecture SAFIRAH of compression is

	signal conca : std_logic_vector (19 downto 0);
   signal a,b,c,d: std_logic_vector (7 downto 0);
	
BEGIN
process (clk,a)
begin

if rising_edge (clk) then
if (busy = '1') then
		not_ready_a <= '0';   --clock
		
		a <= bitin (31 downto 24);
		if (a <= "00100110") then
		   bitout1 <= "00";
		elsif (a = "00100110") then
			bitout1 <= "01";
		elsif (a = "00100110") then
			bitout1 <= "10";
		elsif (a = "00100110") then
			bitout1 <= "11";
	--	else
		--(a = std_logic_vector (63 downto 56) <= (others => '-') then
		--	bitout1 (63 downto 56) <= a;
   	end if;
		end if;
		end if;
	end process;

	
process (clk,b)
begin
if rising_edge (clk) then
	if (busy = '1') then
	not_ready_b <= '0';
	
	 b <= bitin (23 downto 16);
	 if (b <= "11110000") then 
	     bitout2 <= "11110000"; 
	--if (b <= "00100110") then 
		--   bitout2 <= "00";
		--elsif (b <= "00100110") then
			--bitout2 <= "01";
		--elsif (b <= "00100110") then
			--bitout2 <= "10";
		--elsif (b <= "00100110") then
			--bitout2 <= "11";
	   --else
		--bitout2 <= "111100000";
		end if;
		end if;
		end if;
	end process;


process (clk,c)
begin
if rising_edge (clk) then
if (busy = '1') then
	not_ready_c <= '0';
	
	  c <= bitin (15 downto 8);
		if (c <= "11011010") then 
			bitout3 <= "11011010"; 
	--if (c <= "00100110") then
		--   bitout3 <= "00";
	--	elsif (c <= "00100110") then
		--	bitout3 <= "01";
		--elsif (c <= "00100110") then
		--	bitout3 <= "10";
		--elsif (c <= "00100110") then
		--	bitout3 <= "11";
	--	else
		--	bitout3 <= s;
		end if;
	end if;
		end if;
	end process;	


process (clk,d)
begin
if rising_edge (clk) then
if (busy = '1') then
 not_ready_d <= '0';
 
  d <= bitin (7 downto 0);
	if (d <= "00100110") then
		   bitout4 <= "00";
		elsif (d <= "00100110") then
			bitout4 <= "01";
		elsif (d <= "00100110") then
			bitout4 <= "10";
		elsif (d <= "00100110") then
			bitout4 <= "11";
--		else
		--	bitout4 <= s;
		end if;
		end if;
		end if;
	end process;	


--process (clk,e)
--begin
--if rising_edge (clk) then
--if (busy = '1') then
--	not_ready_e <= '0';
	
--	e <= bitin (31 downto 24);
	--if (e <= "00100110") then
	--	   bitout5 <= "00";
	--	elsif (e <= "00100110") then
	--		bitout5 <= "01";
	--	elsif (e <= "00100110") then
	--		bitout5 <= "10";
	--	elsif (e <= "00100110") then
	--		bitout5 <= "11";
	--   else
		--	bitout5 <= s;
--		end if;
--		end if;
--		end if;
--	end process;


--process (clk,f)
--begin
--if rising_edge (clk) then
--if (busy = '1') then
--	not_ready_f <= '0';
	
--	f <= bitin (23 downto 16);
--	if (f <= "00100110") then
--		   bitout6 <= "00";
--		elsif (f <= "00100110") then
--			bitout6 <= "01";
--		elsif (f = "00100110") then
--			bitout6 <= "10";
--		elsif (f <= "00100110") then
--			bitout6 <= "11";
--	   else
		--	bitout6 <= s;
--		end if;
--		end if;
--		end if;
--	end process;


--process (clk,g)
--begin
--if rising_edge (clk) then
--	if (busy = '1') then
--		not_ready_g <= '0';
		
--	g <= bitin (15 downto 8);
--	   if (g <= "00100110") then
--		   bitout7 <= "00";
--		elsif (g <= "00100110") then
--			bitout7 <= "01";
--		elsif (g <= "00100110") then
--			bitout7 <= "10";
--		elsif (g <= "00100110") then
--			bitout7 <= "11";
--	   else
		--	bitout7 <= s;
--		end if;
--		end if;
--		end if;
--	end process;	


--process (clk,h)
--begin
--if rising_edge (clk) then
--	if (busy = '1') then
--		not_ready_h <= '0';
		
--	h <= bitin (7 downto 0);
--	if (b <= "00001000") then 
	--		bitout8 <= "00001000"; 
	--if (h <= "00100110") then
	--	   bitout8 <= "00";
	--	elsif (h <= "00100110") then
		--	bitout8 <= "01";
	--	elsif (h <= "00100110") then
	--		bitout8 <= "10";
	--	elsif (h <= "00100110") then
	--		bitout8 <= "11";
	--	else 
		--	bitout8 <= s;
	--	end if;
	--	end if;
	--	end if;
--	end process;


---------------------concatenation---------------------------------
 
 conca <= bitout1  & bitout2 & bitout3 & bitout4;
-- conca <= conv_std_logic_vector(a,2) & conv_std_logic_vector(b,8) & conv_std_logic_vector(c,8) & conv_std_logic_vector (d,2);	
 
end architecture SAFIRAH;

 

[axcdd]

Because no output depands on it, so synthezer removes this signal as it is useless.

 

[nursafirah]

what do you mean by no output depends on it? can you explain more? :thinker: because the bitout1,bitout2,bitout3 and bitout4 is my output for each process..

 

[verylsi]

You concatanated bitout1 bitout2 bitout3 bitout4 and assigned to a signal Conca... but u never assigned this signal Conca to any of your output , so the conca is never read but assigned in your design , so the synthesis tool will chop this signal while optimizing.
if thr would be an output say
concat_out : out std_logic_vector (19 downto 0) ; in the port definition and
concat_out <= conca; inside the architecture then there wnt be such warning.

 

[nursafirah]

thank you for your help.. it help me to remove the warning.. :smile: