I am not able to see to bit level like a[0] is mapped to what and a[1] is mapped to what. But, On placing mouse pointer on the signal a(1:0), it displays "Input pin: a(1:0) => Signal b,a" in RTL view. I am using Xilinx 12.2 ISE.
So, I feel comp X(.a({b,a}), .b(c)); is correct for the case a[0] => a and a[1] => b and
comp X(.a({a,b}), .b(c)); is correct for the case a[0] => b and a[1] => a.
it may be correct in your case. actually comp X(.a({b,a}), .b(c)) will give different results in definition "input [1:0] a" and "input [0:1] a", so whatever comes in RTL go with it. I always get confused in this.