Somebody has probably already created such a package, I would suggest using Google to try to find it rather than re-inventing it. But if you want to create it from scratch...
1. Define a record type that contains the real and imaginary parts (Note 1)
2. Create function overloads for "+", "-" and "*" (add, subtract and multiply).
3. Define variables or signals of that new record type created in #1
4. Add/subtract/multiply those signals/variables using the new functions that you created in #2. So a signal assignment would look something like this... z <= a+b;
Note 1: If you need this for simulation only and not for synthesis, then the record type would look something like this:
Code:
type t_Complex is record
R: real;
I: real;
end record t_Complex;
If you intend to use this for synthesis, then you cannot use type 'real' for 'R' and 'I'. Instead you will likely want to use fixed point. Google for "VHDL Fixed Point" and you'll run across the package you will need.
Your kidding, right? Or maybe you think your asking something else?
To simulate a VHDL library you use a VHDL simulator, like modelsim, incisive, aldec, etc. on the code you wrote that uses the library functions and types.
libraryIEEE;--use IEEE.STD_LOGIC_1164.ALL;UseIEEE.MATH_REAL.all;useIEEE.Math_complex.all;--use IEEE.STD_LOGIC_unsigned.ALL;--library work;--use work.MATH_COMPLEX.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;entity add isport(x1,x2,y1,y2:inreal;
z1,z2:outreal);end add;architecture Behavioral of add issignal p,q,r:complex;begin
p.RE<=X1;
P.IM<=X2;
Q.RE<=Y1;
Q.IM<=Y2;
R <= P+Q;
Z1<= R.RE;
Z2<=R.IM;end Behavioral;
LIBRARYieee;--USE ieee.std_logic_1164.ALL;--USE ieee.math_real.all;--USE ieee.math_complex.all;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--USE ieee.numeric_std.ALL;ENTITY add_tb ISEND add_tb;ARCHITECTURE behavior OF add_tb IS-- Component Declaration for the Unit Under Test (UUT)COMPONENT add
PORT(
x1 :INreal;
x2 :INreal;
y1 :INreal;
y2 :INreal;
z1 :OUTreal;
z2 :OUTreal);ENDCOMPONENT;--Inputssignal x1 :real;signal x2 :real;signal y1 :real;signal y2 :real;--Outputssignal z1 :real;signal z2 :real;-- No clocks detected in port list. Replace <clock> below with -- appropriate port name --constant <clock>_period : time := 10 ns;BEGIN-- Instantiate the Unit Under Test (UUT)-- uut: add PORT MAP (-- x1 => x1,-- x2 => x2,-- y1 => y1,-- y2 => y2,-- z1 => z1,-- z2 => z2-- );-- Clock process definitions-- <clock>_process :process-- begin-- <clock> <= '0';-- wait for <clock>_period/2;-- <clock> <= '1';-- wait for <clock>_period/2;-- end process;-- -- Stimulus process
stim_proc:processbegin
x1<=25.5;
x2<=25.5;
y1<=21.2;
y2<=22.1;-- hold reset state for 100 ns.waitfor100ms;--wait for <clock>_period*10;-- insert stimulus here wait;endprocess;END;
I want to design hardware following steps:
1. In 16-QAM, find point (a1) with max. metric
2. From a1, find two points (say a2 and a3) with with minimum distance from a1. Now find pt.(say a2) with minimum metric and discard other point
3. From a2, find distance of all points (except a1 and a3) from a2 and repeat step-2.
4. Repeat above steps for all 16 points.