Complex number in vhdl

[NishitVankawala]

How to add, subtract and multiply floating point complex numbers????
i m workin on sphere decoder and have to use complex no. .......
pls..help

 

[K-J]

How to add, subtract and multiply floating point complex numbers????
i m workin on sphere decoder and have to use complex no. .......
pls..help

Somebody has probably already created such a package, I would suggest using Google to try to find it rather than re-inventing it. But if you want to create it from scratch...

1. Define a record type that contains the real and imaginary parts (Note 1)
2. Create function overloads for "+", "-" and "*" (add, subtract and multiply).
3. Define variables or signals of that new record type created in #1
4. Add/subtract/multiply those signals/variables using the new functions that you created in #2. So a signal assignment would look something like this... z <= a+b;

Note 1: If you need this for simulation only and not for synthesis, then the record type would look something like this:

type t_Complex is record
    R:  real;
    I:  real;
end record t_Complex;

If you intend to use this for synthesis, then you cannot use type 'real' for 'R' and 'I'. Instead you will likely want to use fixed point. Google for "VHDL Fixed Point" and you'll run across the package you will need.

Kevin Jennings

 

[NishitVankawala]

Ok....now i have complex package......how to use it?and how to simulate it?

 

[ads-ee]

Ok....now i have complex package......how to use it?

Uh, how about open it in a text editor and see what functions and types it has. Then add it to your design using

library <some_lib_name>;
use <some_lib_name>.all;

and how to simulate it?

Your kidding, right? Or maybe you think your asking something else?
To simulate a VHDL library you use a VHDL simulator, like modelsim, incisive, aldec, etc. on the code you wrote that uses the library functions and types.

 

[TrickyDicky]

there is the ieee package math_complex that defines complex numbers using reals.
They cannot be synthesised, they are for simulation only.

 

[NishitVankawala]

how to enter real inputs in ISIM?
for eg. isim force add a 12 for integer.....

 

[TrickyDicky]

Its would be much easier to write a testbench, rather than force the inputs from ISIM. THen you can do a simple assign:

some_input <= 1.234656.

 

[NishitVankawala]

hey this is a part of my code for complex addition.....can u help me with it...

---

Code VHDL - [expand]
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library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.MATH_REAL.all;
use IEEE.Math_complex.all;
    
--use IEEE.STD_LOGIC_unsigned.ALL;
 
--library work;
 
--use work.MATH_COMPLEX.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity add is
port(x1,x2,y1,y2: in real;
      z1,z2: out real);
end add;
 
architecture Behavioral of add is
signal p,q,r:complex;
begin
p.RE<=X1;
P.IM<=X2;
Q.RE<=Y1;
Q.IM<=Y2;
R <= P+Q;
Z1<= R.RE;
Z2<=R.IM;
 
 
end Behavioral;

---

Test bench

---

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LIBRARY ieee;
--USE ieee.std_logic_1164.ALL;
--USE ieee.math_real.all;
--USE ieee.math_complex.all;
 
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY add_tb IS
END add_tb;
 
ARCHITECTURE behavior OF add_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT add
    PORT(
         x1 : IN  real;
         x2 : IN  real;
         y1 : IN  real;
         y2 : IN  real;
         z1 : OUT  real;
         z2 : OUT  real
        );
    END COMPONENT;
    
 
   --Inputs
   signal x1 : real ;
   signal x2 : real ;
   signal y1 : real ;
   signal y2 : real ;
 
    --Outputs
   signal z1 : real;
   signal z2 : real;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 
 
   --constant <clock>_period : time := 10 ns;
 
BEGIN
 
    -- Instantiate the Unit Under Test (UUT)
--   uut: add PORT MAP (
--          x1 => x1,
--          x2 => x2,
--          y1 => y1,
--          y2 => y2,
--          z1 => z1,
--          z2 => z2
--        );
 
   -- Clock process definitions
--   <clock>_process :process
--   begin
--      <clock> <= '0';
--      wait for <clock>_period/2;
--      <clock> <= '1';
--      wait for <clock>_period/2;
--   end process;
-- 
 
   -- Stimulus process
   stim_proc: process
   begin    
x1<= 25.5;
x2<= 25.5;  
y1<= 21.2;
y2<= 22.1;
      -- hold reset state for 100 ns.
      wait for 100 ms;  
 
      --wait for <clock>_period*10;
 
      -- insert stimulus here 
 
      wait;
   end process;
 
END;

---

But i m not getting my desired result.......

 

[mrflibble]

And what is that desired result?

 

[TrickyDicky]

what exacctly are you expecting - your testbench doesnt instantiate your unit under test (the add component).

 

[NishitVankawala]

I want to design hardware following steps:
1. In 16-QAM, find point (a1) with max. metric
2. From a1, find two points (say a2 and a3) with with minimum distance from a1. Now find pt.(say a2) with minimum metric and discard other point
3. From a2, find distance of all points (except a1 and a3) from a2 and repeat step-2.
4. Repeat above steps for all 16 points.

 

[TrickyDicky]

Sounds like a plan
What problems are you having?