comparison of two LDO structures !!

[liushangpiao]

Hi,all
I am designing a LDO with required output voltage of 3V and current ability of 50mA. There are two structure to choose ,
but i don't know what merit each has.
what difference are between them,and which is better?
Thanks in advance.

 

[svraj]

Hi,

Looks to me the difference between A and B is the Opamp. A is an NMOS input Opamp while B is a PMOS input Opamp.

First, what is your reference voltage that you are using? Anything below 1.2V i would suggest you use B as the PMOS input transistors will be better in receiving a low voltage while maintaining itself in the saturation region for good amplification.

As a summary, B will enable lower input common mode range while A is more suitable for higher input common mode range nearer to supply voltage.

In terms of gain and bandwidth, both can be designed to obtained same results.


Regards,
svraj

 

[imar]

In terms of gain and bandwidth, both can be designed to obtained same results.

svraj

yes they could have the same results but if we do car of noise generated, i think that PMOS configuration will be more advantageous.

another issue:

to compare between these two structures you have to run your simulations to see the impact on line and load regulation, AC response, ...etc
i think this is the best way to choose.

hope to help

regards

imar

 

[gevy]

A is better.
For B:
If load current = 0 than output transistor gate-sorce voltage is near threshold. In this case diff cascade works bad because right transistor is in saturation.

 

[endru]

Yes, A is better.
The output transistor normally has large VGS swing as it is required to drive output current from 0 to some tens or hundreds mA.
Therefore, when your output current is 0, the output transistor's gate-source voltage will be very small. Hence structure B is not suitable.

However, please be minded that even if you use structure A, if your output transistor is pretty huge and your output current is 0, the output transistor can go to subthreshold region and the current mirror's right transistor can go to linear region. So, proper sizing for both the current mirror and the output transistor is required.

 

[liushangpiao]

I believe I get to the bottom of this problem...
Appreciate your kidness very much!