Min geometry would come from whoever's printing it
(wafer fab? silk screen?) and what they know about
manufacturability, reliability.
The 1.8V MOSFET (PMOS) may be your best bet as
a comparison, but perhaps it's more about gate oxide
(dielectric) thickness - you can operate thicker oxide,
5V or higher, FETs at 1.8V and since Cox is a big deal
in channel conductance and gm, matching tox might
be more fair. But the paper I looked through at that
link provided only L, W and no gate thickness I could
see. Your minimum L, for comparo purposes, should be
5um (not 0.18um) or higher - whatever the discussed
gates' ring oscillator performance was based upon,
geometry-wise.
The logic style shown is PMOS depletion-load. Very
similar to the first MOS products, before they got a
handle on the various reliability detractors (PMOS
"walks out" leakage and breakdown while NMOS
"walks in" from hot carrier and mobile ion charge).
Look for info on old-timey PMOS logic and maybe
you will find some interesting side references. But
the
http://opdk.umn.edu/files/AFM10_OFET.pdf
paper looks to have enough circuit detail for you
to replicate their work using silicon PMOS devices.