latch based designs
**broken link removed**
EE Times (07/17/2006 8:00)
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Using pulsed latch instead of flip-flop reduces the dynamic power of the clock network, which can consume half of a chip's dynamic power. Real designs have shown approximately a 20 percent reduction in dynamic power using this methodology.
Pulsed latch concept
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A latch can capture data during the sensitive time determined by the width of clock waveform. If the pulse clock waveform triggers a latch, the latch is synchronized with the clock similarly to edge-triggered flip-flop because the rising and falling edges of the pulse clock are almost identical in terms of timing.
The pulsed latch requires pulse generators that generate pulse clock waveforms with a source clock.
Designing with pulsed latches
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- Pulsed latch replacement and pulse generator insertion
- Skew and slew control of the clock tree
- Timing analysis and optimization
- Power analysis
- Pulse latch design rule checking
Power analysis
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Power analysis must distinguish the pulsed latches and normal flip flops and apply power values appropriately. Moreover, there is additional power consumed in pulse generators and delay cells. These power numbers must be considered during power analysis for comprehensive power savings.
References
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[1] P. Zuchowski, "Design Strategies for Low Power ASICs," IBM Technology Group New England Design Forum, June 18, 2003
[2] Tetsuya Yamada, et.al, "Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core", IEICE Transactions on Electronics 2006 E89-C(3), Pp 287-294