no. Im not talking about code.
A synchronised data signal will be a double registered version of data to avoid meta-stability, assuming its completly asynchronous to the clock (if its synchronous to the clock, then there is no problem.)
You need to do something like this:
Code:signal data_sync : std_logic_vector(1 downto 0); process(clk) begin if rising_edge(clk) then data_sync <= data_sync(0) & data; end if; end process; count_proc : processs(clk) begin if rising_edge(clk) then if data_sync(1) = '1' then count <= count + 1; end if; end if; end process;
Making a process sensitive to data just means you're creating logic sensitive to the data signal (probably without registers). The above code synchronises the data signal and then uses that to measure the time its high for.
library ieee;
use ieee.std_logic_1164.all;
entity counter is
port(
clk : in std_logic;
data : in std_logic;
enable : in std_logic;
dout : out std_logic;
);
end counter;
architecture count of counter is
signal data_sync : std_logic_vector(1 downto 0);
signal pre_count : integer;
signal pre_count_1 : integer;
signal pre_count_2 : integer;
signal data_count : integer;
begin
process(clk)
begin
if rising_edge(clk) then
data_sync <= data_sync(0) & data;
end if;
end process;
count_proc : process(clk, enable)
begin
if (enable = '0') then
data_count <= 0;
elsif (data_sync(1) = '1') then
pre_count <= 0;
end if;
if rising_edge(clk) then
pre_count <= pre_count + 1;
end if;
end process;
if (data_count = 0) then
pre_count_1 <= pre_count;
data_count <= data_count + 1;
elsif (data_count = 1) then
pre_count_2 <= pre_count;
data_count <= data_count - 1;
end if;
compare_proc : process(clk, pre_count_1, pre_count_2)
begin
if rising_edge(clk) then
if (pre_count_1 > pre_count_2) then
dout <= '1';
elsif (pre_count_1 < pre_count_2) then
dout <= '0';
end if;
end if;
end count;
process(clk, reset)
begin
if reset = '1' then
--async reset
elsif rising_edge(clk)
--do sync
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
a <= "000";
a <= "001";
a <= "010";
end if;
end process;
process(clk)
variable a : std_logic_vector(2 downto 0);
begin
if rising_edge(clk) then
a := "000";
op1 <= a;
a := "001";
op2 <= a;
a := "010";
op3 <= a;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
a <= "00";
if ip1 = '1' then
a <= "01";
end if;
if ip2 = '1' then
a <= "11";
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if ip2 = '1' then
a <= "11";
elsif ip1 = '1' then
a <= "01";
else
a <= "00";
end if;
end if;
end process;
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