Comparator threshold for flash inside pipeline ADC

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Hello For pipe line ADC 1.5 bit 2.5 Bit or just regular once as shown bellow.
And i could not find why for 1.5 bit we use comparator, Vref=+- 1/4Vref, or how they choose what should be the output of each stage of the comparator.
They just give those two paramters as a fact.
What is the intution i should use in order to see what VREF and what VOUT i need to put for my comparators in piple ADC?
Thanks.



 
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Output of the comparator is always vdd and gnd, it's a comparator after all. The thresholds of the comparator are chosen such that for a given interstage gain you maximize the offset errors that can be tolerated, because this make the comparator design easier.
 

Hello,how can i see mathematickly that the tollerable offset is maximised?
from what you said earlier the maximal amount is
2Vin-Vr=Vr
Vin=Vr
earlier stage:
2Vin=Vr
Vin=Vr/2
offset = Vr/2-Vr/4=Vr/4

But why its optimised? we can make the central vin range between Vr/2 and -Vr/2 then
offset = Vr/2-Vr/2=0

 

You don't want to have offset 0, because you can not design a comparator with 0 offset. If you allow for bigger offset, the design becomes easier.
Then, if you move the thresholds to +-Vr/2 your gain will have to be different than 2. If you want you can draw this situation.
 

Yes i know that Zerro tollerable offset which we get for Vin=0.5Vr is zero.
regarding easy or optimal.how do i see the optimal threshold value for this comparator?
Thanks.
 

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