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comparator systematic offset effects on flah adc ??

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amic

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I would like to know what effects the systematic offset may have on flash adc ? I know that random offset in comparators worsen INL and DNL errors in adc.

Also if the systematic offset of my cmos comparator is 15 mV; is it 22222222 bad ??
what should i do to optimise it ?

thanks.

Sachin
 

Chethan

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amic said:
I would like to know what effects the systematic offset may have on flash adc ? I know that random offset in comparators worsen INL and DNL errors in adc.

Also if the systematic offset of my cmos comparator is 15 mV; is it 22222222 bad ??
what should i do to optimise it ?

thanks.

Sachin

Refer to the paper
"A 500 kHz 14-bit BiCMOS ADC" by Pinchback, M.A.; Johnstone, K.K.
. Advanced A-D and D-A Conversion Techniques and their Applications, 1994.
 

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