Comparator latency MC

[analogckt]

Hi

I was designing an LVDS RX stage which has a PMOS folded cascode input and NMOS schmitt trigger stages. While doing Monte carlo on the circuit for both process and Mis match, I observed that the output edges vary over a time period (20% of the clock time). How can I reduce this error so that timing margins are not affected? Any help appreciated

Thanks
Ackt

 

[erikl]

Try to find out which parameter variation(s) (vth ?) mainly affect the propagation delay time - then you can venture for design counter action.