What do you mean by "platform" methodology? Are you talking about chip-design with standard-cell ASIC?
If so, then most companies go with the foundry's recommendation. For example, TSMC has a 'reference design flow' for all its major logic process-nodes (130nm, 90nm, 65nm, etc.) The reference-design flow includes special step-by-step instructions for synthesizing the netlist, running milestone checks (LINT, equivalency, design-for-test, timing, clock-skew, etc.), and the recommended ways to deal with implementation issues. For example, if you have a signal-intergrity issue, the reference design flow recommends which tools to use, to fix the SI issue.
It has been a long time since I looked at that stuff. Customers are not REQUIRED to follow the reference-flow exactly, and many don't. But your question is a million dollar question, because a full front-end to back-end setup requires huge investment in tools, engineer resources, and time. It's not like a company will get the reference design manual, buy all the tools tomorow, and then tape-out a working chip the following day. (If only it were that easy...)