KD494
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Hi everyone,
I'm trying to figure out my expected throughput using this fast ethernet controller and having a conceptual problem more than anything else.
https://www.mouser.com/ds/2/495/ksz8851snl_ds-242556.pdf
So the part claims to be able to support 100Mb/sec communication and I calculated the overhead (preamble, header, frame check, interpacket gap) to be about 1.86% of that leaving me with 98.14Mb/sec. However the source of these bits would be the SPI bus which can only be clocked up to 40MHz. My understanding of SPI tells me that it provides 1bit/clk cycle and would therefore only be able to provide 40Mb/sec under ideal conditions.
Is the 100Mb/sec rating just a maximum that the hardware can handle? Is it attainable in practice? I just don't see how you could utilize the full speed of fast ethernet with such a slow SPI clock.
Thanks!
I'm trying to figure out my expected throughput using this fast ethernet controller and having a conceptual problem more than anything else.
https://www.mouser.com/ds/2/495/ksz8851snl_ds-242556.pdf
So the part claims to be able to support 100Mb/sec communication and I calculated the overhead (preamble, header, frame check, interpacket gap) to be about 1.86% of that leaving me with 98.14Mb/sec. However the source of these bits would be the SPI bus which can only be clocked up to 40MHz. My understanding of SPI tells me that it provides 1bit/clk cycle and would therefore only be able to provide 40Mb/sec under ideal conditions.
Is the 100Mb/sec rating just a maximum that the hardware can handle? Is it attainable in practice? I just don't see how you could utilize the full speed of fast ethernet with such a slow SPI clock.
Thanks!