Common mode fully differential OpAmp

[Fabien]

Hi everyone,

I redesign a fully differential OpAmp for switched capacitor integrator. (My last post: Fully differential OTA design for low power SC integrator).
The inputs are PMOS, in order to have a larger unity-gain frequency (K. Martin's book). The thing is that I can't have a common mode at Vdd/2. I don't know how to design in order to get the output at Vdd/2, it's always 0.5V whatever the current, W, L of the transistors...

Any suggestions??

Thank you

 

[yuvan]

Hi Fabien,

Its highly unlikely for you to get output common mode as vdd/2. The bottom NMOS are proper current sources & its nearly impossible to match the pmos & nmos current sources (considering channel length modulation) unless cmfb circuit is employed.

 

[Fabien]

I did a CMFB circuit, but on the top at the PMOS in top of the differential input. Maybe I should do it at the bottom current mirror? Let's try it...

- - - Updated - - -

Actually nothing change. I agree that is should be unlikely to get Vdd/2, but most of papers or books used this kind of design, just wondering how to size..

thank you

 

[nitishn5]

You might be able to get a common mode of Vdd/2 by appropriate sizing and also using CMFB.
You cannot fix the common mode without using CMFB otherwise it would vary with corners.

Another option is to have a second stage. It would be easy to use CMFB to get Vdd/2.

 

[Fabien]

You cannot fix the common mode without using CMFB otherwise it would vary with corners.

You're right! but I did a CMFB, and the results is the same. I also designed a 2 stages, same thing. (see attached). And with

You might be able to get a common mode of Vdd/2 by appropriate sizing and also using CMFB.

OK, that's the question. How to size, is there a tricky manner? I change Ws, Ls, and got the same results...

thanks

 

[nitishn5]

Are you sure your CMFB is doing its job?
Try this procedure :
1. Force the outputs at the desired voltage levels ie Vdd/2 using voltage sources. Ensure that each device is in the proper region of operation here.
2. Note the gate voltage of the tail current source at the above ckt and design the CMFB such that it gives a little more(or less depending on whether you are driving NMOS or PMOS) this voltage, ie ensure the CMFB would be able to give proper drive to the current source. (Do not connect the CMFB now.)
3. Now that both the amplifier and the CMFB are designed, connect the CMFB loop and run!

By sizing, I mean that you would have to size such that the Vout is at Vdd/2 while keeping enough headroom for every transistor. It would crunch the headroom for the input pair and the tail current source. You would have to give big sizes for those.

 

[Fabien]

Thank you for your help!! I change the design a little bit with a current mirror OTA. The CMFB is switched capactors. I got 60dB in differential mode with a 1.2MHz GBW! (with only a few hundreds of nA!)
The output is swinging around Vdd/2 (a bit less). Hopefully the CMFB circuit is working cause I got almost the same results without it.
Anyway, thank you for your guidances.