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Common Mode feedback under Corner Analysis

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moisiad

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Hi
I have designed a discreate time common mode feedback for an Opamp dedicated for a DAC.

Although the Common mode voltage is well defined (VDD/2) when i am doing corner analysis varies significantly. Have anyone of you noticed such an effect?
Is it excpected or my CMFB circuit is not well designed?If it is expected how critical is for the ADC performance
 

How much is the VDD? Does all the switch work on triode or shutdown mode?
 

VDD is 1V. I will also check if some devices enter triode region in corner analysis
 

I suggest that the CMFB circuit should be simulated under corner analysis first,make sure that the gain of this part is not sensitive of corners and no mosfets get into triode region under any corner.
 

During corner analysis no transistor enters triode region.
However CM output voltage varies from 0.3 to 0.6V (0.5V is for the nominal case).
 

Generally,CMFB contains a OPAMP,I guess that your OPAMP'gain is not high enough,perhaps it's less than 10 now.

As I mentioned above,I suggest that you should do a ac analysis on the CMFB part,make sure the gain is high and stable in spite of corners.
 

What is corner analysis?

I have never heared about!
 

Corner analysis refers to the analysis (AC, DC, Transient) done for different transistor models, temperature and power supply ranges in order to cover all possible worst and best cases.
 

does the common voltage of input make the first stage work on sat. region?
 

Hi all

I think that we are very close to the solution. I have inserted a CMFB circuit also in the first stage (except from the output stage). Now the voltages are stabilized.

You see in fact the problem was in the first stage, which in turn affected the second. My conclusion is that for low voltages (1V) a CMFB circuit only in the output is not enough.

However i dont now if this extra CMFB circuit deteriorates some other parameters (except power dissipation)

Thanks for your remarks
 

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