Common centroid/Interdigitized layout LVS issue

[samisilicon]

I am new to the idea of common centroid layout. Although I have studied various configurations of common centroid layout of differential pairs but every time I try implementing a configuration I get LVS errors. I have some basic questions to ask about common centroid layout design which I hope will help many other beginners as well.

1) Let me have a differential pair (A & B) with 20um/1um size of each MOS, now I want to implement the simplest possible configuration of interdigitization.i.e ABBA. I want to know to create two instances of A do I have to use multiplier or finger parameter of the MOS or shall I manually create 4 MOS each with size 10um/1um? When I use multiplier or finger parameter it gives only one solid instance in the layout with multiple drains/sources/gates or gates respectively.

2) Therefore I manually use 4 different MOS and simulate them in schematics. See the figure (cc1) below. To implement the configuration ABBA, I import all the four instances and create the layout as shown in cc2. But it gives LVS errors saying devices do not cross match. Why do parallel MOS with all terminals connected give us LVS errors? Am I following the right procedure for common centroid layout?


3) Please help!

 

[lamoun]

Hello,

First, your problem has nothing to do with common centroid. LVS cannot understand if you used such a technique.
1)Using multiplier must give you multiple objects. I have not encountered this before. Generally I use a mix of multiplicity and fingers.

2) You haven't connected the bulk of the transistors. You must add a contacts for the n-wells.
Did this layout passed a DRC test?

 

[samisilicon]

Hello,

First, your problem has nothing to do with common centroid. LVS cannot understand if you used such a technique.
1)Using multiplier must give you multiple objects. I have not encountered this before. Generally I use a mix of multiplicity and fingers.

2) You haven't connected the bulk of the transistors. You must add a contacts for the n-wells.
Did this layout passed a DRC test?

Yes the layout is DRC passed. You are right about the bulk contacts; they are definitely missing in my layout. Adding them solved the issue of LVS. But multiple parameter only gives you one instance (a big MOS sliced into smaller ones, all having drain, source and gate but connected as one unit).

 

[erikl]

... one instance (a big MOS sliced into smaller ones, all having drain, source and gate but connected as one unit).

So this one MOSFET instance is already fingered, which makes sense for a large W/L ratio. It saves you to instance very wide MOSFETs, so achieves a better aspect ratio, which is good for low mismatch.

BTW: Common centroid design does not mean total mirror symmetry. Drains/sources should always be positioned at the same side for both transistors to be matched.