Common Centroid & Interdigitization

[kansalgagan]

common centroid resistor

for the critical circuits,we prefer centroid matching as it nulls any differences in both X and Y direction..and for normal circuits we can go with interdigitation matching.

 

[faizalism]

current flow in common centroid

what about for high speed differential circuits, it is difficult to design by using centroid for differential circuit. is it ok by just using symmetryical layout.

thanks,

 

[protonixs]

common centroid interdigitization difference

what about for high speed differential circuits, it is difficult to design by using centroid for differential circuit. is it ok by just using symmetryical layout.

thanks,

use
A B A B
B A B A
in high speed circuits.
the wiring is not the top priority; you should consider the flow of current.
in the technique shown above, the flow of current is in one direction.
always follow step symmetry and not mirror symmetry because the latter is deceiving. and of course observe the distance between the gates.
and lastly, dont connect dummies to the part where the AC characteristic of the diff pair could be disturbed.

Added after 15 minutes:

If drain or source is shared in common centroid, the layout could be very compact as well. For current mirror with common centroid, gate connection can be very easy.

in my experience of high speed ckts, drain-source sharing is avoided.

 

[krisdpeterson]

inter-digitization

Hi,

In my design I have a current mirror supplying bias currents to different parts of the circuit. The current mirror has 6 transistors in it. Trying to draw a matching structure to fit all 6 would be difficult, but for a few it is critical that they are matched. I saw in an earlier post on this topic that normally for these current mirrors one would use interdigitization, but I was wondering if I have transistors A B C D E and F, where the matching between B and C and between E and F is especially critical, would it be ok to lay them out like this (with maybe dummies on the sides):

ABCDEF
ACBDFE

Kind regards,
kris

 

[layoutmaster]

common-centroid & layout

Hi Kris...

Question: Which one is the diode connected transitor?

Added after 2 minutes:

In other words, let's guess A is the Diode connected transistor, I would do:

DUM B C D A E F DUM
or
DUM B D C A F E DUM

 

[krisdpeterson]

unit cell in common centroid

Hi,

thanks for the quick reply! Yes, A is the diode connected transistor. But is there any reason for the two orders you suggested placing them? Also I see you wrote "OR" between your two rows. Does that mean you think it is not necessary to lay them out common-centroid-like in two rows reversing the order that B and C and E and F are placed in the two rows?

thanks again,
kris

 

[layoutmaster]

what is common centroid

So you do not have 6, you have 6 M=2 (12 transistors...) Now I understand...

My or was becuase, with 6 transistors, by placing the diode in the middle, both alternatives were the same... but if you have M=2 I would say change my OR by an AND and the answer is YES, it would be better to crosscouple each of the pairs with critical matching and having the diode in the middle of them in order to also make a good current copy...

 

[krisdpeterson]

common centroid site:edaboard.com

Hi,

Thanks again. By the way, I wanted to say that your last two posts were helpful, but it doesn't have a button for that. Do you have to start a new thread to be able to say someone's post was helpful?

Anyway, actually as far as M is concerned, I don't really understand how that is decided. In my schematic, I have been simulating using single transistors. But I've seen in one of my books (unfortunately I don't have the book at home with me so I can't tell you exactly what it says) that it is useful when matching large transistors to break them into different strips (and the book gave an equation for determining how many). The bias currents needed by the different parts of the circuit are different so each of those transistors A,B,C,D,E, and F, have the same L but Ws that are integer multiples of the smallest W (E and F are the same size and actually have the smallest Ws). B and C are the largest (but not the same size). I simplified by breaking them each into 2, but actually, B and C will need several strips if they are to have the same W as the other strips. But I was hoping I could still do something like I said, where I cross-couple B's and C's strips and put the others on the sides. A and D are the same size, and I can increase E and F to be the same size as A and D. But I was thinking of making strips where Wstrip=1/2 E's (and F's) W and breaking up B and C into the required number of strips and then intertwining them. I have to check when I get in tomorrow, but if I remember right A=D=2*E=2*F and B=5*E and C=10*E. Or is it possible to do something like this:

DUM BC A1 D1 E DUM
DUM CB A2 D2 F DUM

where BC and CB are actually multiple fingers of each mixed up. Thinking about it now, I see I may need to change B so it is an even multiple of E if I want to do the layout in this way, but is this ok? Or am I misunderstanding something important about layout?

regards,
kris

 

[layoutmaster]

common centroid to match current mrror

OK. Let's go by parts.

What you mention about your book is saying is like that, obviously, but is REALLY important. THe split of big MOSes that need good matching into smaller "unit cells" to be interdigitated is KEY and has to do with a main goal: to minimize the statistical error on the output current.

Having said this, the next step is to define the UNIT CELL (a mos with smaller W, and as square as possible) in order to be able to create ALL the rest of the currents by combination of this unit cell. In other words, it's a good layout practice (more if you require matching) to have identical devices (even when one coudl be M=1 and other M=10, the idea is to have the same W and L). Last (but far from being least) for good matching forget about having min. lenght MOS.

Added after 2 minutes:

Regarding your comment about the helpful posts, I'm glad to hear that. Thank you.

Probably you'll need to use the BLUE botton reporting the post... I guess it's not only for bad or abuse reporting...

 

[kumarans]

Hai Guys,
I have one dout
which below mentioed pattern is good and avoid the gradient and offset voltage??????????

ABAB ABBA
BABA vs. BAAB
ABAB BAAB
BABA ABBA

Rgds
Kumaran.S

 

[jadiyappagoudar]

HI Guys,

Recently i have done a layout for high speed differential Amplifier wherein, parasitics on the output nodes ( drain of input pair ) and input nodes ( gates of inut pair ) were utmost important to have minimum values possible.

I had A = 20 fingers and B = 20 fingers. I neither did a common centroid nor cross coupled matching ( Since both of these matching would add parasitics ). All i had done is, kept all A fingers on one ( left ) side and all B fingers on another ( right side ). Here there wont be any crossings of Drain connections of A and B. Since there is no cross talking of A drain and B drain, the parasitics on these nodes would be minimum.

Since the area of entire matching set ( A and B fingers together ) was not large enough, there wouldnt be much gradient across the matching set. Both A and B fingers would see relatively same environment.

Regards,
Vijayanand M J