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Comments on VCO Design

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micasa

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Hi everyone,

I am designing a conventional complementary LC VCO using CMOS 0.18 um technology. Vdd = 1.8 V, L = 2.9 nH, Q =7.8, f = 1.9 Ghz

I have a problem which I do not understand.

According to this paper "Design Issues in CMOS Differential LC Oscillators", Ali Hajimiri and T. H. Lee, IJSSC, 1999, my VCO has already worked in the

voltage-limited regime (see the waveform of the drain currents) resulting in phase noise degradation. However, DC current is only 1 mA (power

consumption of the core is 1.8 mW), and I cannot increase the current if I consider the waveform of drain currents. In published papers, DC current

usually ranges from several milliampere to 10 mA (in the above paper, DC current is 4 mA, Vdd = 1.5V)

Do I misunderstand this point in Hajimiri's paper?

If not, how can I increase the DC current to several milliampere without pushing the VCO into the voltage-limited regime?

Thanks in advance,

Best regards,

Micasa,
 

mobil

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I think the main issue of keep your VCO out of voltage-limited regime
is that you have to guarantee your tank voltage amplitude not "significantly exceed Vdd" (Hajimiri's paper).

So may you rise DC voltage or carefully caculate the voltage in your tank at
design frequency.(there maybe a tradeoff between the region you want and making your oscillator works)

Hope I don't confuse you.

Goodluck.
 

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