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lsa1961 said:I'm thanking of all for your answers.
One more question.
What do you use for on-chip debugging of the your NIOS based systems?
@ltera's solution: ByteBlasterMV download cable + RedHat's command line debugger.
Will that work well?
Will I need in the FS2's solution: in-target system analyzer + Accelerated Technology's code|lab Debug tool?
Comment it, please.
ddr said:normally you can't synthesise your nios-vhdl/verilog-design after you compile it in synplify. this is because sopc builder puts low-level, architecture specific stuff in the vhdl/verilog which synplify wrongly translates.
a simple solution is to change the target device in sopc builder into flex10ke.
after that you should be able to compile and synthesise without any problem!