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Comments on NIOS-core (Altera)

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lsa1961

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NIOS-core

Does anyone use NIOS-core (Altera)?
Your comment, please?
 

manitooo

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versatil

I love it and it works well

U can put any peripherals U want (if Ur FPGA have enough place of course)

U chose the amout of RAM, ROM, nbr of UART, SPI, TIMER, IO...
U have speciale peripheral to link to SRAM, FLASH....

And you can write Ur own peripherale within the micro or out of the NiOS, but wihtin the chip or moreover offchip (like external ROM... or ADC)

well, I like it very much

I use it on a APEX20K600E and for the moment I use :
16K ROM (where I put my code)
8K RAM
1 UART
1 32bits PIO
1 9 bit PIO
2 4 bit PIO
2 2bits PIO

But I am going to put an other UART and some other extra IO :)

Well in resuming : it's really fun and versatil
 

hcet

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i agree to the text above. also, altera has lowered their prizes for developement boards.
 

ddr

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compile your Nios system with Synplify, Leonardo Spectrum,..

normally you can't synthesise your nios-vhdl/verilog-design after you compile it in synplify. this is because sopc builder puts low-level, architecture specific stuff in the vhdl/verilog which synplify wrongly translates.
a simple solution is to change the target device in sopc builder into flex10ke.
after that you should be able to compile and synthesise without any problem!

happy nios-ing!
ddr
 

Vonn

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?

Wxcuse me but can i know what is NIOS-core
 

dsp_

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hi everybody
how much place/gates does it use?
I ordered the UP2 with a flex10k70 is it possible to use a minimal version of nios on it?
:?:

EDIT: question useless i found the answer in the depths of altera =)
for those who are interested here it is ...
http://www.altera.com/literature/an/an178.pdf
@->a

thanks
dsp_
 

manitooo

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about 1500 to 2000 Logic element for simple NiOS design

I have another question to whom use it

I have defined a ROM (from 0x0000 to 0x3FFF) and a RAM (from 0x4000 to 0x4FFF)

But in my nios firmware, when I do a simple malloc(), it resturn me a pointer on the ROM zone : quiet strange isn't it?

does anybody have already encountered this bug ?

If so, how can I correct it :)
(my FAE is really out of my problem)

plz help :)
THX
 

lsa1961

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I'm thanking of all for your answers.
One more question.
What do you use for on-chip debugging of the your NIOS based systems?
Altera's solution: ByteBlasterMV download cable + RedHat's command line debugger.
Will that work well?
Will I need in the FS2's solution: in-target system analyzer + Accelerated Technology's code|lab Debug tool?
Comment it, please.
 

ddr

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lsa1961 said:
I'm thanking of all for your answers.
One more question.
What do you use for on-chip debugging of the your NIOS based systems?
@ltera's solution: ByteBlasterMV download cable + RedHat's command line debugger.
Will that work well?
Will I need in the FS2's solution: in-target system analyzer + Accelerated Technology's code|lab Debug tool?
Comment it, please.
I suggest you buy the Nios kit for $995 (or less). So you can try it for yourself.
I personally only use the command line debugger, because that suffices for me. If you work on complex designs, I can understand you want to use the third-party tools.

regards,
ddr
 

phoenixfeng

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NIOS-core

is there any url to download nios
 

cawan

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NIOS-core

Nios core is flexible to be configured in sopc builder. Each of the major component is able to be loaded and reconfigure for dedicated application design. The source code of Nios 3.1 is visible as .v or .vhd but starting Nios II, the source code of cpu.v or cpu.vhd is already encrypted. You need to pay more to generate a full .sof file, instead of a time-limited file.
 

RemyMartin

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Re: compile your Nios system with Synplify, Leonardo Spectru

ddr said:
normally you can't synthesise your nios-vhdl/verilog-design after you compile it in synplify. this is because sopc builder puts low-level, architecture specific stuff in the vhdl/verilog which synplify wrongly translates.
a simple solution is to change the target device in sopc builder into flex10ke.
after that you should be able to compile and synthesise without any problem!

happy nios-ing!
ddr
Setting the target device to flex10ke in SOPC builder??? What to do next?
Set flex10ke in SOPC builder-->Generate it----->synthesisi in synplify while set the target device to ???----->compile it in quartusii and set target device to Cyclone or some device else?
 

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