Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
compile your Nios system with Synplify, Leonardo Spectrum,..
normally you can't synthesise your nios-vhdl/verilog-design after you compile it in synplify. this is because sopc builder puts low-level, architecture specific stuff in the vhdl/verilog which synplify wrongly translates.
a simple solution is to change the target device in sopc builder into flex10ke.
after that you should be able to compile and synthesise without any problem!
I'm thanking of all for your answers.
One more question.
What do you use for on-chip debugging of the your NIOS based systems?
Altera's solution: ByteBlasterMV download cable + RedHat's command line debugger.
Will that work well?
Will I need in the FS2's solution: in-target system analyzer + Accelerated Technology's code|lab Debug tool?
Comment it, please.
I'm thanking of all for your answers.
One more question.
What do you use for on-chip debugging of the your NIOS based systems?
@ltera's solution: ByteBlasterMV download cable + RedHat's command line debugger.
Will that work well?
Will I need in the FS2's solution: in-target system analyzer + Accelerated Technology's code|lab Debug tool?
Comment it, please.
I suggest you buy the Nios kit for $995 (or less). So you can try it for yourself.
I personally only use the command line debugger, because that suffices for me. If you work on complex designs, I can understand you want to use the third-party tools.
Nios core is flexible to be configured in sopc builder. Each of the major component is able to be loaded and reconfigure for dedicated application design. The source code of Nios 3.1 is visible as .v or .vhd but starting Nios II, the source code of cpu.v or cpu.vhd is already encrypted. You need to pay more to generate a full .sof file, instead of a time-limited file.
Re: compile your Nios system with Synplify, Leonardo Spectru
ddr said:
normally you can't synthesise your nios-vhdl/verilog-design after you compile it in synplify. this is because sopc builder puts low-level, architecture specific stuff in the vhdl/verilog which synplify wrongly translates.
a simple solution is to change the target device in sopc builder into flex10ke.
after that you should be able to compile and synthesise without any problem!
Setting the target device to flex10ke in SOPC builder??? What to do next?
Set flex10ke in SOPC builder-->Generate it----->synthesisi in synplify while set the target device to ???----->compile it in quartusii and set target device to Cyclone or some device else?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
