[SOLVED] command line that dont work in simulation

Hi
I just wrote some program in vhdl(using only behavioral code), i wanted that the program will work only in simulation.
But the funny thing that happened is that the code is synthesizeble without errors or warnings.
But than i simulate its not doing whats it's supposed to do.
after a few simulation i realized that there is one line of code that the program not doing!!!
Ill post the code and highlight the line that is not being done, perhaps i missing something (although its been synthesized without warnnings).
Im must say that i new to vhdl. and know only basic stuff, i dont know how to do a test bench. i just going to the isim and forcing values and clock(im sure i doing it right ).
Will apriciate any help.
thanks

Hello,

it is not a problem of "not working" simulation. In VHDL signals that occur in processes do not get updated before the entire process is being analyzed (upon an event, in your case the clock). This is because signals assignments in processes are just scheduled to happen. So, be aware of this when writing and simulating code because it can give you unexpected behavior; instead, you can use variables that get updated immediately.

Also, there are several nice tutorials on the Internet about writing test benches in VHDL, like the following:

https://www.embeddedrelated.com/showarticle/31.php

Cheers

romikot said:

Hi
I just wrote some program in vhdl(using only behavioral code), i wanted that the program will work only in simulation.
But the funny thing that happened is that the code is synthesizeble without errors or warnings.
But than i simulate its not doing whats it's supposed to do.
after a few simulation i realized that there is one line of code that the program not doing!!!
Ill post the code and highlight the line that is not being done, perhaps i missing something (although its been synthesized without warnnings).

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;


entity bindiv is
    Port ( mispar : in  STD_LOGIC_VECTOR (4 downto 0);
           mehalek : in  STD_LOGIC_VECTOR (4 downto 0);
           moza : out  STD_LOGIC_VECTOR (4 downto 0);
			  reset: in std_logic;
           clk : in  STD_LOGIC);
end bindiv;

architecture Behavioral of bindiv is
signal hishuvim : std_logic_vector (8 downto 0) :=(others => '0');
signal mikum : integer range 4 downto 0 :=4 ;
constant CONST_MISPAR : std_logic_vector (4 downto 0) := "10101";
begin
process(clk)
begin
if clk'event and clk='1' then
	if reset='1'  then
		hishuvim(4 downto 0)<=mispar;  -- when reset occurs, you should not use input. Take a constant
		hishuvim(4 downto 0)<=CONST_MISPAR; 
		hishuvim(8 downto 5)<=(others => '0');
		mikum<=4;
      moza<=(others => '0'); -- should also be initialized
	else
		--if mehalek>hishuvim(8 downto 4) then -- always true, because every unsigned value is > 0
		if mehalek<hishuvim(8 downto 4) then
			moza(mikum)<='0';
		else  -- was never used in your code
			moza(mikum)<='1';
			hishuvim(8 downto 4)<=hishuvim(8 downto 4)- mehalek(4 downto 0);--this line isnt working 		
end if;
		  -- Otherwise your counter mikum runs out of range (mikum <= -1), therefore Fatal error
		   if mikum > 0 then
		      mikum<=mikum-1;
                   end if;      
		   hishuvim <= hishuvim(7 downto 0) & '0';
	end if;
end if;
end process;	
end Behavioral;

Click to expand...

What is the code for? What did you want to do? Can you describe it please?
Feel free to ask, if you need more support.