Combining block symbol files in Quartus II

[h@ro]

In one of my designs I use a block symbol which I created from a verilog module- It has an output which gets passed through a divider block (from the megafunctions library) and the result is fed back into the module. How can I make these into a single block for the sake of simplicity?

 

[ads_ee]

As I don't use the block symbols I may be way off base here...

Couldn't you have instantiated the megafunction divider inside the verilog module you wrote? Then if you generated a new block symbol for your module it wouldn't have the divider connection (as it's inside the block.

 

[h@ro]

As you suggested, it looks like instantiating the block explicitly inside the verilog module is the way to go. I'm just having a problem now getting the division to simulate correctly (it only synthesises to a few percent of what a 32 bit divider should, so the divider isnt being synthesised for some reason). I generally connect modules via the graphical editor, so I'm not sure of a few things. The following is an example code from altera literature regarding instantiating megafunctions in HDL modules. Do the values being connected to altfp_mult have to be wires? or could wire_dataa and datab be declared as reg values?

module MF_top (a, b, sel, datab, clock, result);
input [31:0] a, b, datab;
input clock, sel;
output [31:0] result;
wire [31:0] wire_dataa;
assign wire_dataa = (sel)? a : b;
altfp_mult inst1 (.dataa(wire_dataa), .datab(datab), .clock(clock),
.result(result));
defparam
inst1.pipeline = 11,
inst1.width_exp = 8,
inst1.width_man = 23,
inst1.exception_handling = "no";
endmodule

 

[ads_ee]

You should really use less antiquated Verilog syntax. Try using Verilog 2001 syntax instead.

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
module MF_top (
  input   [31:0]    a,        // add comment
  input   [31:0]    b,        // add comment
  input   [31:0]    datab,    // add comment
  input             sel,      // add comment
  input             clock,    // add comment
  output  [31:0]    result    // add comment
);
 
  // add comment, wire is the correct type
  wire    [31:0]    wire_dataa = sel ? a : b;
 
  // add comment
  altfp_mult  #(
    .pipeline           (11),
    .width_exp          (8),
    .width_man          (23),
    .exception_handling ("no")
  ) inst1 (
    // note this will also work
    //.dataa    (sel ? a : b),
    .dataa    (wire_dataa),
    .datab    (datab),
    .clock    (clock),
    .result   (result)
  );
 
endmodule

---

Besides the coding style, have you checked the synthesis log to see if something is being removed that you expect to stay in the design? From you're description of the problem you're missing some connection somewhere that is allowing Quartus to strip out logic. Possibly something is inadvertently a constant value? Without more of the design it's hard to determine.

 

[h@ro]

The code wasn't actually mine- just copied straight out of an altera technical publication as an example of what I was trying to do (though the formatting didn't copy across). - but I tried assigning all the reg values I was using to wires to connect to the ports of the divider module being instantiated, and then everything worked and synthesised correctly. It makes sense that only wires can connect ports now that I think about it. Thanks for the help!