Say I have signal with "pseudo-random" pulse and another signal with repeating pulse (like clock).. How do I combine those into one digital signal in verilog? Assuming they are both generated with the same clock (minimum pulse width is the same).
I think the question is more about basic Verilog logic design...
How do you use an always statement or what is an assign statement. How do you use those statements to make logic.
Code Verilog - [expand]
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// Code to describe an AND gate// using an always blockalways@(a, b)begin// you can code this with always @* begin instead.
out = a & b;// note use of blocking assignment, =end// using assignassign out = a & b;// DFF following the AND gatealways@(posedge clk)begin
out <= a & b;// note use of non-blocking assignment, <=end