I tried to upload the result of the simulation when I began this threat, but I could not. below pic is the result of the simulation(I tried three times to upload it successfully).Hi,
first things first:
What do expect the circuit to do? Obviously oscillate. But at which frequency?
Then you talk about the transitor to be ON and OFF. But in this circuit I doubt the bjt is meant to be completely ON/OFF. I rather think it generatees some distorted sine shape. So continously current flow through collector, but continously rising and falling --> oscillating.
You talk about V_B2, V_E2, I_C2 ... but you don´t give values. Please show the simulation results.
For my taste the inductance is very low, it needs a very high speed current rise to generate a useful voltage across the inductance.
Klaus
What now is the problem?I tried to upload the result of the simulation when I began this threat, but I could not. below pic is the result of the simulation(I tried three times to upload it successfully).
also, the circuit simulation shows an oscillation. the below pic is a very small part of the simulation.
No answer?first things first:
What do expect the circuit to do? Obviously oscillate. But at which frequency?
I believe that none of this relevant.Hi,
No answer?
***
So what are you worried about?
The current of IC (Q1) vs V_BE?
There are several specifications in the datasheet. (Sadly you did not post a link. Thus I used the ON Semiconductor one. )
Do you understand the specifications:
* Output capacitance
* Input capacitance
* Delay time
* Rise time
* Storage time
* Fall time
.. and what this means in a circuit?
Klaus
Hi,
No answer?
***
So what are you worried about?
The current of IC (Q1) vs V_BE?
There are several specifications in the datasheet. (Sadly you did not post a link. Thus I used the ON Semiconductor one. )
Do you understand the specifications:
* Output capacitance
* Input capacitance
* Delay time
* Rise time
* Storage time
* Fall time
.. and what this means in a circuit?
Klaus
I think a bjt has current when vbe is larger than 0.6-0.7, but in this simulation, I saw that when vbe<0.6, there is current from collector to emitter. I want anyone to clear this with me and explain why there is a current when vbe<0.6.Hi,
No answer?
***
So what are you worried about?
The current of IC (Q1) vs V_BE?
There are several specifications in the datasheet. (Sadly you did not post a link. Thus I used the ON Semiconductor one. )
Do you understand the specifications:
* Output capacitance
* Input capacitance
* Delay time
* Rise time
* Storage time
* Fall time
.. and what this means in a circuit?
Klaus
hi, thanks for your replyThe finer details of Colpitts, Clapp and other Sinewave BJT Oscillators
- Here I compare two methods of LC sine oscillators with 1 inductor.
- The ideal 50% of max amplitude is partially regulated by Vbe nonlinear pulse load so Vo is not a regulated amplitude (no AGC).
- Beware of negative effects on hFE, Vcc noise and load resistance in each case below.
- The base resistance controls current and voltage gain as well as Zc/Ze impedance ratio.
- The most stable clean sine wave is when gain is just slightly greater than unity (1) and Vo is roughly 50% (undistorted) of max Vpp swing (distorted).
- In both cases the oscillator is basically a pulse of base current then it resonates with high Q. so distortion must be regulated by carefully controlling loop gain just enough to sustain oscillation plus 10% or so for tolerances. Too much gain will cause saturation effects on one half of the sine wave peak.
- The gain also refers to the level of the Ib base current pulse relative to the sine current. (see scope simulation from Falstad site)
- Both are hFE sensitive but since these oscillators are pinged by pulses to Vbe, they are suitable for high GBW transistors with very low hFE (e.g. = 10)
- To scale frequency 1st choose an impedance value for 1/sqrt(LC)*f*2pi, this examples X(f)~ 1kohm then choose each L,C value.
1. Positive Feedback (+FB) method uses a smaller cap say 10% of C1 resonant cap to emitter to boost amplitude in phase.
- Inductor L on Vcc permits a double max amplitude distorted output at Vcc+/- Vcc.
- But since it has higher || Q it is much higher output impedance, but also better supply noise immunity. the emitter is biased to only produce pulse current at low duty cycles on peak then float open circuit.
- This is a common base (CB) amp with the Vb at constant voltage and Ve modulated by the tiny pulse per cycle from negative peak of Vc (out), which pulses Vbe to inject current for L||C to ring with high Q.
2. Negative Feedback (-FB or NFB) method uses two caps of equal value thus equivalent resonant C is C/2 or the equivalent value if mismatched, but optimal performance is usually matched.
This is a common emitter (CE) amp with DC gain Rc/Re but AC gain boost by Re bypass cap. Then Rfb feedback improves sine quality, lowers output impedance and controls attenuated of NFB to get gain just slightly greater than unity. Unfortunately, all Vcc noise is passed to output, reduced slightly by the amount of NFB. But the clear advantage is a much lower output impedance = Rc so the load will affect output amplitude but not the Q of the resonator buffered by the transistor gain from base resonance signal.
View attachment 186743
Since the CE amp increases gain with hFE, using NFB means more fedback signal and thus reduces the output level.
Normally one chooses the next stage impedance much greater (e.g. 10x) than the output impedance of these amplifiers and AC couples if DC offset must be removed.
Here is my comparison simulation for 3.3V. To use a large supply all R values are typically scaled up and keep similar ratios.
These are fundamentals and not the optimal design found in more complex designs used in signal generators, but they are simple.
hiI guess ... if I asked a third time ... it would not make you answer my queastions.
So I better don´t waste our both time.
Klaus
Current is exponential with Vbe so there is current continuously even at Vbe =0.5 but to make with work follow my design rules and see how Vbe is almost constant at 630 mV with a pulse that double the sine base current from 80 uA pk to 160 uA with the pulse to excite resonance.hi
in a bjt, if vbe<0.6 then is it possible that there is Ic? If your answer is positive in which condition? For example, if vbc is forward and vbe<0.6, is it possible that there is ic?
Ic yes, but no gain.in a bjt, if vbe<0.6 then is it possible that there is Ic? If your answer is positive in which condition? For example, if vbc is forward and vbe<0.6, is it possible that there is ic?
Common-base mode operates the transistor by increasing or reducing voltage of the emitter leg instead of changing bias at the bias terminal. It's just another method of changing the b-e relationship, in order to alter the transistor's conduction.why there is a current when vbe<0.6.
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