cordic processor
hi,
u could try out either way actually. the fft algorithm i guess u would know is available on different compromising parameters.. reg. power, speed, pipeline depth etc.. u could use ur desired architecture. u could refer to the "inside fft blackbox" by crc press for that.. incase u dont know..
1) u could implement the algorithm in C, then use "celoxica" a vlsi software which could be used to convert the C program to synthesisable VHDL/Verilog code. i havent tried workin on it.. but iu have seen in their home page. /http://www.celoxica.com
2) similarly, the software from mentor graphics, CATAPULT does the same thing, but in addition it gives the flexibility of getting the synthesisable codes for both ASIC and FPGA. i have tried very simple programs on this..
I would also like to say, this aint at first easy coz. u ll hav to spend lots of time in getting acquaintence with the environment. and moreover, they have specific commands in addition to the ordinary c++ program u would use... also, there are certain steps to be followed while writing the code. u must be a master peice in C coding.. then it would be easy. nevertheless, u would enjoy workin in it.
and the otherway, writing direct VHDL code... reg. that.. there are many open cores available at
www.opencores.org... u could check them out. incase, u have some specified architecture which u feel u would like to implement to compromise on some parameter.. then pls post it.. so that any help could be rendered.. hope the reply was usefull...
/cedance