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Coding help in Verilog

Thread starter josephine1234
Start date Dec 1, 2017

Status: Not open for further replies.

Dec 1, 2017

#1

J

josephine1234

Junior Member level 1

where must i include the file required for readmemb command in verilog

Dec 1, 2017

#2

dpaul

Advanced Member level 5

Not inside any synthesizable design. So it should be in the test-bench.

Dec 1, 2017

#3

J

josephine1234

Junior Member level 1

how do i include any file in the test bench?

Dec 1, 2017

#4

dpaul

Advanced Member level 5

Read a good Verilog book. Search online for tutorials.
It is very basic stuff.

**broken link removed**

Dec 1, 2017

#5

J

josephine1234

Junior Member level 1

ive already gone through the site u mentioned.. thanks!

Status: Not open for further replies.

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