[SOLVED] code style problem: too many signal delays?

[naught]

I have tried the single process FSM to code, after reading many posts that suggest that`s the better way. But I come across some problems, for I have to delay certain signals...all the time.
say if I want to manipulate some RAMs. To make RAMs work, I have to delay the address signal, to match the first rising edge of the enable ena and wea signal(that is, the address 0 would be occurring at the clk with ena and wea rise to 1).
This could really get complex and confused, because there are so many signals to be delayed, when using RAMs at different layers.

it`s very inconvenient, and the problem is that I spend most of the time, when coding vhdl, on figuring out which signal should be delayed, rather than arithmetic stuff...
please help. thanks in advance.

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Code VHDL - [expand]
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process(clk,rst)
    begin
        if(rst = '1') then
            pr_state <= s0;
            cnt3584 <= 0;
            addr2048 <= 0;
            addra_ram14336 <= 0;
        elsif(rising_edge(clk)) then
            case pr_state is
                when s0 =>
                    if(start = '1') then
                        pr_state <= s1;
                    else
                        pr_state <= s0;
                    end if;
                    ena_ram3584 <= '0';
                    wea_ream3584 <= "0";
                    ena_ram14336 <= '0';
                    wea_ram14336 <= "0";
                when s1 =>
                    if(cnt3584 = 3583) then
                        cnt3584 <= 0;
                    else
                        cnt3584 <= cnt3584 + 1;
                    end if;
                    if(cnt3584 = 3583) then
                        pr_state <= s2;
                    else
                        pr_state <= s1;
                    end if;
                    cnt3584_d1 <= cnt3584;
                    ena_ram3584 <= '1';
                    wea_ream3584 <= "1";
                when s2 =>                      
                    ena_ram3584 <= '0';
                    wea_ream3584 <= "0";
                    ena_ram14336 <= '1';    -- enable ram14336,  1 clk delay.
                    wea_ram14336 <= '1';
                    if(addr2048 = 2047) then
                        addr2048 <= 0;
                    else
                        addr2048 <= addr2048 + 1;
                    end if;
                    if(addra_ram14336 = 14335) then  
                        addra_ram14336 <= 0;
                    else
                        addra_ram14336 <= addra_ram14336 + 1;
                    end if;
                    if(addra_ram14336 = 14335) then   --RAM14336 address, needs to delay 2 clk.
                        pr_state <= s0;
                    else
                        pr_state <= s2;
                    end if;                 
            end case;
            ena_ram14336_d1 <= ena_ram14336;
            wea_ram14336_d1 <= wea_ram14336;
            addra_ram14336_d1 <= addra_ram14336;
            addra_ram14336_d2 <= addra_ram14336_d1;
        end if;         
    end process;

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[TrickyDicky]

Yes. This is the nature of the design. You need to pipeline the design to get control path length matching. You could just delay the state and have the control signals act on the delayed state variable rather than delay all the control signals.

Welcome to the world of pipelining. You'll spend more time debugging this than the arithmatic. The maths is the easy bit!