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| library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_counter is
port (
clk : in std_logic;
up_count : in std_logic;
count : out unsigned(15 downto 0)
);
end bcd_counter;
architecture behavior of bcd_counter is
signal temp : unsigned(15 downto 0);
signal a0 : unsigned(3 downto 0) := "0000";
signal a1 : unsigned(3 downto 0) := "0000";
signal a2 : unsigned(3 downto 0) := "0000";
signal a3 : unsigned(3 downto 0) := "0000";
begin
process(clk)
begin
if clk = '1' and clk'event then ---1
if up_count = '1' then ---2
if a3 <= to_unsigned(9, 4) then ---3
if a2 <= to_unsigned(9, 4) then ---4
if a1 <= to_unsigned(9, 4) then ---5
if a0 <= to_unsigned(9, 4) then ---6
a0 <= a0 + to_unsigned(1, 4);
temp <= to_unsigned(1000*(to_integer(a3)) + 100*(to_integer(a2)) + 10*(to_integer(a1)) + 1*(to_integer(a0)) + 1, 16);
if a0 = to_unsigned(9, 4) then
a1 <= a1 + to_unsigned(1, 4);
a0 <= "0000";
end if;
if a1 = to_unsigned(9, 4) and a0 = to_unsigned(9, 4) then-- and temp >= to_unsigned(99, 16) and temp <= to_unsigned(999, 16)then
a2 <= a2 + to_unsigned(1, 4);
a1 <= "0000";
a0 <= "0000";
end if;
if a2 = to_unsigned(9, 4) and a0 = to_unsigned(9,4) then--and temp >= to_unsigned(999, 16) and temp <= to_unsigned(9999, 16) then
a3 <= a3 + to_unsigned(1, 4);
a2 <= "0000";
a1 <= "0000";
a0 <= "0000";
end if;
end if; ---6
end if; ---5
end if; ---4
end if; ---3
end if; ---2
end if; ---1
end process;
end behavior; |