verilog if else simulate mux
Multiple styles of coding. e.g.
Using if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
1What are the advantages / disadvantages of each coding style shown above?
2How Synthesis tool will give result for above codes?
3What happens if default statement is removed in case statement?
4What happens if combination 11 and default statement is removed?
Here there is no difference between the two codes, the output is the same, as well the priority is not taken into consideration in the above logic, prioritycomes under different conditions, when the above control signals are different, what i mean to say is when one statement is used for different select signal and the other used for different select signal then priority comes under picture.
Here as u r mentioning all the the possibilities of the two signals that is 00, 01, 10, 11 then there is no difference, there is difference when u r using a full case and a parallel case
hope it is understandable
regards