doromdor
Newbie level 3
Sorry if this is not the correct place to post my question,
I am intrested in co-simulation of VHDL and systemC
I want to use VHDL testbench in order to test systemC files
The programs I am using for this are Questasim and Modelsim (of mentor graphics)
Anyone has a good tutorial about this or can explain me how it is done ?
Thanks in advance ,
Dor
I am intrested in co-simulation of VHDL and systemC
I want to use VHDL testbench in order to test systemC files
The programs I am using for this are Questasim and Modelsim (of mentor graphics)
Anyone has a good tutorial about this or can explain me how it is done ?
Thanks in advance ,
Dor