Dec 7, 2009 #1 D doromdor Newbie level 3 Joined Nov 17, 2009 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,312 Sorry if this is not the correct place to post my question, I am intrested in co-simulation of VHDL and systemC I want to use VHDL testbench in order to test systemC files The programs I am using for this are Questasim and Modelsim (of mentor graphics) Anyone has a good tutorial about this or can explain me how it is done ? Thanks in advance , Dor
Sorry if this is not the correct place to post my question, I am intrested in co-simulation of VHDL and systemC I want to use VHDL testbench in order to test systemC files The programs I am using for this are Questasim and Modelsim (of mentor graphics) Anyone has a good tutorial about this or can explain me how it is done ? Thanks in advance , Dor
Dec 7, 2009 #2 F farhada Advanced Member level 2 Joined Oct 1, 2004 Messages 587 Helped 84 Reputation 168 Reaction score 30 Trophy points 1,308 Location Nice, France Activity points 5,025 What is the simulator you are using? And what do you do with the DUT model?
Dec 8, 2009 #3 D doromdor Newbie level 3 Joined Nov 17, 2009 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,312 hello pini1 , I need to use modelsim with vhdl testbench which are given to me so writing systemC testbench is not an option. thanks anyway farhada , I am using modelsim as a simulator and I am not quite sure what you mean with DUT model. if you can please explain I will be grateful Dor
hello pini1 , I need to use modelsim with vhdl testbench which are given to me so writing systemC testbench is not an option. thanks anyway farhada , I am using modelsim as a simulator and I am not quite sure what you mean with DUT model. if you can please explain I will be grateful Dor
Dec 13, 2009 #4 A aji_vlsi Advanced Member level 2 Joined Sep 10, 2004 Messages 643 Helped 85 Reputation 170 Reaction score 12 Trophy points 1,298 Location Bangalore, India Activity points 4,944 Dor, Look at their manual, I found: VHDL Instantiating SystemC We have Verilog/SV-SystemC training examples @ CVC, can quickly make it to VHDL if needed. Contact me offline info@cvcblr.com if interested. Good luck Ajeetha, CVC www.cvcblr.com
Dor, Look at their manual, I found: VHDL Instantiating SystemC We have Verilog/SV-SystemC training examples @ CVC, can quickly make it to VHDL if needed. Contact me offline info@cvcblr.com if interested. Good luck Ajeetha, CVC www.cvcblr.com