Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

CMOS voltage swing problem

Status
Not open for further replies.

gstekboy

Member level 5
Joined
Oct 18, 2013
Messages
87
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
512
I modelled an XOR gate using HSPICE (Transistor level).Input voltage signal is 4V and Vdd of the circuit is 5V (threshold voltage= 1v).
While giving input voltage 4v I got Maximum output voltage swing as 5v, So my problem is I cant cascade the output of this XOR gate(5v) with another XOR gate beacause it will turn off cascaded transistors.

How to overcome the problem?
 

gstekboy

Member level 5
Joined
Oct 18, 2013
Messages
87
Helped
1
Reputation
2
Reaction score
1
Trophy points
8
Activity points
512
Output swing is 5V.
How will that turn off cascaded transistors?

When gate voltage of PMOS 5v and Source voltage (Vdd) of PMOS 5v,the transistor will be in cut off.
 

Audioguru

Advanced Member level 5
Joined
Jan 19, 2008
Messages
9,211
Helped
2,128
Reputation
4,250
Reaction score
1,955
Trophy points
1,393
Location
Toronto area of Canada
Activity points
57,862
Don't you want the Pmos to turn on and off?
When its gate and source are both +5V then it is off. When the source is still +5V but its gate is 0V then it is turned on. What is the problem?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top