CMOS Technology is LOW POWER?

[asnprabhu]

technology like cmos

Why CMOS technology is called as low power?

 

[hung_wai_ming@hotmail.com]

cmos technology

CMOS logic is driven by voltage instead of current like bipolar technology, so there is no base current required. This is already one factor for power reduction.
CMOS can be easily shrunk from say 1.0um to 0.18um or even 0.09um, so the parasitic cap is shrunk easily, so switching current is reduced, further for power reduction.
CMOS logic is rail-to-rail, so reduction of threshold voltage in PMOS and NMOS helps voltage supply required, so 3.3V in 0.35um down to 1.8V in 0.18um, therefore further reduce switching current, power consumption further reduced.
Leakage current is normally much less except deep submicron from 0.18um

 

[rfsystem]

SORRY!

The argument that CMOS is low power is not correct. It is the circuit architecture for logic circuit which made the wrong conclusion that CMOS is lower power.

The detailed reason is that with complementary devices the

RATIO of STATIC to DYNAMIC Current could be made very low. Similar to the typical digital circuit and system usage where the edge trip in 20ps but the period is only 2ns. So up to a static/dynamic current ratio of 0.01 everthing is fine. If the static consumption increase the circuit power is dominated by static power.

The complementary circuits could be also made with complementary bipolar. The leakage is already lower so the ratio is better.

At 45nm S/D and gate leakage dominate and multigate tech must be used. At this time the cost advantage of MOS versus Bipolar decrease. I finally see special devices made of bipolar mechanism but looking like MOS to preserve the low static/dynamic ratio.

 

[hung_wai_ming@hotmail.com]

Basically, I agree to your agrument.
What I thought was a general idea most of the time CMOS logic should be comparatively having low power consumption compared with other technologies if we are talking about same logic functions, so actually, this question is too wide to discuss here, however, one thing is quite certain, over the past 30 years, except nowadays in very deep submicron technologies (we are not talking about leakage here), if you want to have minimal sleep mode current or standby current for a circuit, CMOS is always the best.

 

[asnprabhu]

Hey I agree with u

Digital circuits have very large dynamic currents

Can you plz clearly explain the static current?

 

[hung_wai_ming@hotmail.com]

In terms of logic operationg,
"dynamic" means logic is toggling
"static" means logic is stable at one state.

"static" current could mean when one logic is stable, the current it consumed itself
and to the load. If the load is resistive, then you know the result. If the load is capacitive, then it will not have static current except leakage

"dynamic" current could mean switching current charging/discharging the internal parasitic cap to effect the logic to change from one state to another. Also, includes the shoot-thru current during the transition and somehow it may dominate if the design fails to be good

 

[asnprabhu]

thanks a lot for the above info


When we talk abt a CMOS digital circuit (simple inverter)? How can we say that it is a low power?

Is it because of high dynamic currents? ( high dynamic currents can be expected because large variation in the input voltage in a short period of time)


I didnt get the static current concept actually, will it be low when compared to dynamic current?
why is this?

 

[eternal_nan]

There is a flaw to the BJT vs. CMOS argument presented above: BJTs are still trailing by a factor of 10x in integration densities, so even doing a comparison between BJT and CMOS for digital circuit power consumption is invalid. If BJTs were scaled to similar sizes as CMOS currenty is (45nm) static currents would rise in a manner comparable to what was seen in CMOS, that is if BJTs can be even made to work in those geometries.